Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process
Errata
Specification Update 33
AE42. Simultaneous Access to the Same Page Translation Entries by Both
Cores May Lead to Unexpected Processor Behavior
Problem: When the following conditions occur simultaneously, this may create a rare internal
condition which may lead to unexpected processor behavior.
One core is updating a page table entry, including the processor setting the
Accessed and/or Dirty bits in the PTE as the result of an access
The other core is using the same translation entry.
Implication: Unpredictable behavior in the processor may lead to livelock and shutdown. Intel has
not observed this erratum with any commercially-available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE43. IO_SMI Indication in SMRAM State Save Area May Be Lost
Problem: The IO_SMI bit in SMRAM‟s location 7FA4H is set to "1" by the CPU to indicate a
System Management Interrupt (SMI) that occurred as the result of executing an
instruction that read from an I/O port. Due to this erratum, the setting of the IO_SMI
bit may be lost. This may happen if following the instruction that read from an I/O
port, there is an instruction with a memory operand that results in one of the
following:
Update of a Page Table Entry (PTE) Accessed (A) or Dirty (D) bits.
Page Fault (#PF)
A REP I/O read
Unaligned Memory access where either address of the first or last byte of the
access (e.g., (Address1stByte AND NOT 0x3F) OR (AddressLastByte AND NOT
0x3F)) is equal to the address in one of the Debug Address Registers (DR0-
DR3) (e.g., DRx AND NOT 0x3F ) as long as any address breakpoint is enabled
through the Debug Control Register (DR7).
Implication: SMI handlers may not be able to identify the occurrence of I/O SMIs.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AE44. Logical Processors May Not Detect Write-Back (WB) Memory Writes
Problem: Multiprocessor systems may use polling of memory semaphores to synchronize
software activity. Because of this erratum, if a logical processor is polling a WB
memory location while it is being updated by another logical processor, the update
may not be detected.
Implication: System may livelock due to polling loop and undetected semaphore change. Intel has
not observed this erratum on commercially-available systems.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.