Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 31
AE37. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE38. BTS Message May Be Lost When the STPCLK# Signal Is Active
Problem: STPCLK# is asserted to enable the processor to enter a low-power state (C2, C3,
etc.). Under some circumstances, when STPCLK# becomes active, a pending BTS
(Branch Trace Store) message may be either lost and not written or written with
corrupted branch address to the Debug Store area.
Implication: BTS messages may be lost in the presence of STPCLK# assertions.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE39. Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management Are Inaccurate
Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-7FH may have
inaccurate results up to ±7.
Implication: There may be a small error in the affected counts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.