Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Electrical Specifications
40 Datasheet
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
CCP
referred to in these specifications refers to instantaneous V
CCP
.
3. Reserved.
4. Measured at 0.1*V
CCP
.
5. Measured at 0.9*V
CCP
.
6. For Vin between 0 V and V
CCP
. Measured when the driver is tristated.
7. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#,PWRGOOD. No package parasitics are included.
8. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Measured at 0.2*V
CCP
.
3. V
OH
is determined by value of the external pullup resistor to V
CCP
. Please contact your Intel representative
for details.
4. For Vin between 0 V and V
OH
.
5. Cpad includes die capacitance only. No package parasitics are included.
§
Table 13. CMOS Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes
1
V
CCP
I/O Voltage 1.0 1.05 1.10 V
V
IL
Input Low Voltage CMOS -0.1 0.0 0.33 V 2, 3
V
IH
Input High Voltage 0.7 1.05 1.20 V 2
V
OL
Output Low Voltage -0.1 0 0.11 V 2
V
OH
Output High Voltage 0.9 V
CCP
1.20 V 2
I
OL
Output Low Current 1.3 4.1 mA 4
I
OH
Output High Current 1.3 4.1 mA 5
I
LI
Input Leakage Current ±100 µA 6
Cpad1 Pad Capacitance 1.8 2.3 2.75 pF 7
Cpad2 Pad Capacitance for CMOS Input 0.95 1.2 1.45 pF 8
Table 14. Open Drain Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes
1
V
OH
Output High Voltage 1.0 1.05 1.10 V 3
V
OL
Output Low Voltage 0 0.20 V
I
OL
Output Low Current 11.40 50 mA 2
I
Leak
Output Leakage Current ±200 µA 4
Cpad Pad Capacitance 1.8 2.3 2.75 pF 5