Datasheet

Datasheet 25
Electrical Specifications
3.8 CMOS Signals
CMOS input signals are shown in Tabl e 4 . Legacy output FERR#, IERR# and other non-
AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for more than four BCLKs in order
for the processor to recognize them. See Section 3.10 for the DC specifications for the
CMOS signal groups.
3.9 Maximum Ratings
Ta b le 5 specifies absolute maximum and minimum ratings. If the processor stays within
functional operation limits, functionality and long-term reliability can be expected.
Caution: At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long term reliability can be
expected. At conditions exceeding absolute maximum and minimum ratings, neither
functionality nor long term reliability can be expected.
Caution: Precautions should always be taken to avoid high-static voltages or electric fields.
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2. Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits does not affect the long term reliability of the device. For
functional operation, please refer to the processor case temperature specifications.
3. This rating applies to the processor and does not include any tray or packaging.
4. Failure to adhere to this specification can affect the long-term reliability of the processor.
Table 5. Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
1
TSTORAGE
Processor storage
temperature
-40 85 °C 2, 3, 4
V
CC
Any processor supply voltage
with respect to V
SS
-0.3 1.55 V
V
inAGTL+
AGTL+ buffer DC input
voltage with respect to V
SS
-0.1 1.55 V
V
inAsynch_CMOS
CMOS buffer DC input
voltage with respect to V
SS
-0.1 1.55 V