Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
46 Specification Update
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AE82. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H)
counts transitions from x87 Floating Point (FP) to MMX™ technology instructions. Due
to this erratum, if only a small number of MMX™ technology instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX technology
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE83. A WB Store Following a REP STOS/MOVS of FXSAVE May Lead to
Memory-Ordering Violations
Problem: Under certain conditions, as described in the Software Developers Manual section
"Out-of-Order Stores For String Operations in Pentium
®
4, Intel
®
Xeon
®
, and P6
Family Processors", the processor may perform REP MOVS or REP STOS as write
combining stores (referred to as “fast strings”) for optimal performance. FXSAVE may
also be internally implemented using write combining stores. Due to this erratum,
stores of a WB (write back) memory type to a cache line previously written by a
preceding fast string/FXSAVE instruction may be observed before string/FXSAVE
stores.
Implication: A write-back store may be observed before a previous string or FXSAVE related store.
Intel has not observed this erratum with any commercially available software.
Workaround: Software desiring strict ordering of string/FXSAVE operations relative to subsequent
write-back stores should add an MFENCE or SFENCE instruction between the
string/FXSAVE operation and following store-order sensitive code such as that used for
synchronization.
Status: For the steppings affected, see the Summary Tables of Changes.
AE84. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from
System Management Mode) may cause the lower two bits of CS segment register to
be corrupted.