Intel® StrongARM® SA-1100 Microprocessor Developer’s Manual August 1999 Order Number: 278088-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 4 4.1 4.2 5 5.1 5.2 Introduction......................................................................................................................1-1 Intel® StrongARM® SA-1100 Microprocessor .................................................. 1-1 Overview............................................................................................................ 1-4 Example System.................................................................
5.2.11 5.2.12 5.2.13 5.2.14 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 iv Registers 10 – 12 RESERVED............................................................. 5-6 Register 13 – Process ID Virtual Address Mapping.............................. 5-7 Register 14 – Debug Support (Breakpoints)......................................... 5-8 Register 15 – Test, Clock, and Idle Control .......................................... 5-9 Caches, Write Buffer, and Read Buffer...........................
9 9.1 9.2 9.3 9.4 9.5 System Control Module ...................................................................................................9-1 General-Purpose I/O.......................................................................................... 9-1 9.1.1 GPIO Register Definitions..................................................................... 9-2 9.1.1.1 GPIO Pin-Level Register (GPLR) ............................................ 9-3 9.1.1.2 GPIO Pin Direction Register (GPDR) ..........
9.6 10 10.1 10.2 10.3 10.4 10.5 vi 9.5.3.6 Booting After Sleep Mode...................................................... 9-29 9.5.3.7 Reviving the DRAMs from Self-Refresh Mode ...................... 9-30 9.5.4 Notes on Power Supply Sequencing .................................................. 9-30 9.5.5 Assumed Behavior of an SA-1100 System in Sleep Mode................. 9-30 9.5.6 Pin Operation in Sleep Mode.............................................................. 9-32 9.5.
10.6 10.7 10.8 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 10.5.3 DRAM Access Followed by a Refresh Operation ............................. 10-25 PCMCIA Overview........................................................................................ 10-26 10.6.1 32-Bit Data Bus Operation............................................................... 10-27 10.6.2 External Logic for PCMCIA Implementation ................................... 10-28 10.6.3 PCMCIA Interface Timing Diagrams and Parameters ............
11.8 viii 11.7.5.1Lines Per Panel (LPP) ......................................................... 11-36 11.7.5.2Vertical Sync Pulse Width (VSW) ........................................ 11-36 11.7.5.3End-of-Frame Line Clock Wait Count (EFW)....................... 11-37 11.7.5.4Beginning-of-Frame Line Clock Wait Count (BFW) ............. 11-37 11.7.6 LCD Controller Control Register 3 .................................................... 11-39 11.7.6.1Pixel Clock Divider (PCD).................................
11.9 11.8.3.1UDC Disable (UDD)............................................................. 11-64 11.8.3.2 UDC Active (UDA) .............................................................. 11-64 11.8.3.3Bit 2 Reserved ..................................................................... 11-64 11.8.3.4Endpoint 0 Interrupt Mask (EIM).......................................... 11-64 11.8.3.5Receive Interrupt Mask (RIM)............................................. 11-64 11.8.3.6Transmit Interrupt Mask (TIM) .....
11.9.2 11.9.3 11.9.4 11.9.5 11.9.6 11.9.7 11.9.8 11.9.9 x 11.9.1.5Data Field ............................................................................ 11-81 11.9.1.6CRC Field ............................................................................ 11-81 11.9.1.7Baud Rate Generation ......................................................... 11-81 11.9.1.8Receive Operation ............................................................... 11-82 11.9.1.9Transmit Operation ..............................
.10 11.9.9.5Receive Transition Detect Status (RTD) (read/write, noninterruptible)................................................ 11-99 11.9.9.6End of Frame Flag (EOF) (read-only, noninterruptible)................................................. 11-99 11.9.9.7CRC Error Status (CRE) (read-only, noninterruptible)............................................... 11-100 11.9.9.8Receiver Overrun Status (ROR) (read-only, noninterruptible)............................................... 11-100 11.9.
11.11 xii 11.10.10.4Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt).......................................... 11-122 11.10.10.5Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt).......................................... 11-122 11.10.10.6Framing Error Status (FRE) (read/write, nonmaskable interrupt) ................................... 11-123 11.10.11HSSP Status Register 1 ................................................................ 11-124 11.10.11.
11.12 11.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt).......................................... 11-139 11.11.7.3Receiver Idle Status (RID) (read/write, maskable interrupt) ......................................... 11-140 11.11.7.4Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt) ................................... 11-140 11.11.7.5Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)11-140 11.11.7.
11.12.6.1Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt).......................................... 11-163 11.12.6.2Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt).......................................... 11-163 11.12.6.3Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt).......................................... 11-164 11.12.6.4Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrupt)............
11.13 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 15 15.1 15.2 16 16.1 16.2 16.3 11.12.12.1Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)............................................... 11-181 11.12.12.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptibl11-181 11.12.12.3SSP Busy Flag (BSY) (read-only, noninterruptible)............................................... 11-181 11.12.12.4Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt).......
.4 16.5 16.6 16.7 Instruction Register.......................................................................................... 16-2 Public Instructions ........................................................................................... 16-2 16.5.1 EXTEST (00000) ................................................................................ 16-3 16.5.2 SAMPLE/PRELOAD (00001) ............................................................. 16-3 16.5.3 CLAMP (00100) ..............................
Figures 1-1 1-2 2-1 2-2 2-3 5-1 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 SA-1100 Features.............................................................................................. 1-1 SA-1100 Example System................................................................................. 1-5 SA-1100 Block Diagram ......
11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 13-1 13-2 13-3 14-1 14-2 16-1 16-2 16-3 16-4 16-5 HP-SIR Modulation Example ....................................................................... 11-104 UART Frame Format for IrDA Transmission (<= 115.2 Kbps) .................... 11-105 4PPM Modulation Encodings ...................................................................... 11-105 4PPM Modulation Example ................................................
10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 12-1 12-2 12-3 13-1 13-2 14-1 14-2 16-1 DRAM Memory Size Options......................................................................... 10-14 DRAM Row/Column Address Multiplexing .................................................... 10-14 Peripheral Control Modules’ Register Width and DMA Port Size .................... 11-2 Peripheral Units’ Base Addresses ........................
1 Introduction 1.1 Intel® StrongARM® SA-1100 Microprocessor The Intel® StrongARM® SA-1100 Microprocessor (SA-1100) is the second member of the StrongARM® family. It is a highly integrated communications microcontroller that incorporates a 32-bit StrongARM® RISC processor core, system support logic, multiple communication channels, an LCD controller, a PCMCIA controller, and general-purpose I/O ports.
Introduction Table 1-1. Features of the SA-1100 CPU for AA and EA Parts • High Performance — 150 Dhrystone 2.1 MIPS @ 133 MHz — 220 Dhrystone 2.1 MIPS @ 190 MHz • Low power (normal mode)† • • • • 3.3 V I/O interface 208-pin thin quad flat pack (LQFP)†† 256 mini-ball grid array (mBGA) 32-way set-associative caches — <230 mW @1.5 V/133 MHz — 16 Kbyte instruction cache — <330 mW @ 1.5 V/200 MHz — 8 Kbyte write-back data cache • Integrated clock generation — Internal phase-locked loop (PLL) — 3.
Introduction Table 1-3. Changes to the SA-1100 Core from the SA-110 • Data cache reduced from 16 Kbyte to 8 Kbyte • Interrupt vector address adjust capability • Read buffer (nonblocking) • Minicache for alternate data caching Table 1-4.
Introduction 1.2 Overview The SA-1100 Microprocessor (SA-1100) is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache, an 8 Kbyte write-back data cache, a minicache, a write buffer, a read buffer, and a memory management unit (MMU) combined in a single chip. The SA-1100 is software compatible with the ARM™ V4 architecture processor family and can be used with ARM support chips such as I/O, memory, and video.
Introduction The instruction set comprises eight basic instruction types: • Two make use of on-chip arithmetic logic unit, barrel shifter, and multiplier to perform high-speed operations on data in a bank of 16 logical registers (31 physical registers), each 32 bits wide. • Three classes of instructions control data transfer between memory and the registers: one optimized for flexibility of addressing, one for rapid context switching, and one for swapping data.
Introduction 1.4 ARM™ Architecture The SA-1100 implements the ARM V4 architecture as defined in the ARM Architecture Reference, 28-July-1995, with the following options: 1.4.1 26-Bit Mode The SA-1100 supports 26-bit mode but all exceptions are initiated in 32-bit mode. The P and D bits do not affect the operation of SA-1100; they are always read as ones and writes to them are ignored. 1.4.2 Coprocessors The SA-1100 supports MCR and MRC access to coprocessor number 15.
Introduction 1.4.6 Write Buffer The SA-1100 has an eight-entry write buffer with each entry able to contain 1 to 16 bytes. A drain write buffer operation is supported. 1.4.7 Read Buffer The SA-1100 has a four-entry read buffer capable of loading 1, 4, or 8 words of data per entry. This facility permits software to preload data into the buffer for use at a later time without blocking the operation of the processor. Software can flush either a single entry or the entire buffer (four entries).
Functional Description 2 This chapter provides a functional description of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100). It describes the basic building blocks within the processor, lists and describes the pins, and explains the memory map. 2.1 Block Diagram The SA-1100 consists of the following functional blocks: • Processor The processor is the ARM™ SA-1 core with a 16 Kbyte instruction and 8 Kbyte data cache (Dcache).
Functional Description Figure 2-1 shows the functional blocks contained in the SA-1100 integrated processor. Figure 2-2 is a functional diagram of the SA-1100. Figure 2-1. SA-1100 Block Diagram Intel® StrongARM®* SA-1100 Instruction 3.686 MHz OSC 32.
Functional Description 2.2 Inputs/Outputs Figure 2-2.
Functional Description 2.3 Signal Description The following table describes the signals. Key to Signal Types: n – Active low signal IC – Input, CMOS threshold ICOCZ – Input, CMOS threshold, output CMOS levels, tristatable OCZ – Output, CMOS levels, tristatable Table 2-1. Signal Descriptions (Sheet 1 of 3) Name A<25:0> Type OCZ Description Memory address bus. This bus signals the address requested for memory accesses. Bits 21..
Functional Description Table 2-1. Signal Descriptions (Sheet 2 of 3) Name Type Description L_FCLK OCZ LCD frame clock. L_LCLK OCZ LCD line clock. L_PCLK OCZ LCD pixel clock. L_BIAS OCZ LCD ac bias drive. TXD_C OCZ CODEC transmit. RXD_C IC CODEC receive. SCLK_C OCZ CODEC clock. SFRM_C OCZ CODEC frame signal. UDC+ OCZ Serial port zero transmit pin (UDC). UDC- IC Serial port zero receive pin (UDC). TXD_1 OCZ Serial port one transmit pin (SDLC).
Functional Description Table 2-1. Signal Descriptions (Sheet 3 of 3) Name 2-6 Type Description nRESET_OUT OCZ Reset out. This signal is asserted when nRESET is asserted and deasserts when the processor has completed resetting. nRESET_OUT is also asserted for "soft" reset events (sleep and watchdog). nTRST IC Test interface reset. Note this pin has an internal pull-down resistor and must be driven high to enable the JTAG circuitry.
Functional Description 2.4 Memory Map Figure 2-3 shows the SA-1100 memory map. The map is divided into four main partitions of 1 Gbyte each. The bottom partition is dedicated to static memory devices (ROM, SRAM, and Flash) and to the PCMCIA expansion bus area. It occupies addresses 0h0000 0000 through 0h3FFF FFFF. This space is divided into four 128 Mbyte blocks for static memory devices and two 256 Mbyte blocks for PCMCIA. The static memory space is intended for ROM, SRAM, and Flash memory.
Functional Description Figure 2-3.
ARM™ Implementation Options 3 The following sections describe ARM™ architecture options that are implemented by the Intel® StrongARM® SA-1100 Microprocessor (SA-1100). 3.1 Big and Little Endian The big endian bit in the control register sets whether the SA-1100 treats words stored in memory as being stored in big endian or little endian format. Memory is viewed as a linear collection of bytes numbered upwards from 0. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 hold the second, and so on.
ARM™ Implementation Options transfer the whole 32-bit value, and not just the flag or control fields. When multiple exceptions arise simultaneously, a fixed priority determines the order in which they are handled. The priorities are listed later in this chapter. Most exceptions are fully defined in the ARM Architectural Reference. The following sections specify the exceptions where the SA-1100 implementation differs from the ARM Architectural Reference. SA-1100 initiates all exceptions in 32-bit mode.
ARM™ Implementation Options 3.2.3 Abort An abort can be signalled by the internal memory-management unit, through a data breakpoint, or by a reference to reserved memory. An abort indicates that the current memory access cannot be completed or that a prespecified breakpoint address and (optionally) data pattern has been reached.
ARM™ Implementation Options 3.2.4 Vector Summary Table 3-1 lists byte addresses, and they normally contain branch instructions pointing to the relevant routines. These addresses (except the reset vector) can be changed (to 0xFFFF xxxx) through the vector adjust facility (bit 13, register 1, coprocessor 15). The vector adjust is cleared at reset and cannot modify the reset vector. Table 3-1. Vector Summary Address 3.2.
ARM™ Implementation Options 3.2.6 Interrupt Latencies and Enable Timing The ability to recognize an IRQ or FIQ interrupt is, in part, determined by the I and F bits of the CPSR. To ensure that a pending interrupt is taken, an interrupt-enabling write to CPSR (msr instruction) must be separated from an interrupt-disabling write to the CPSR by at least two instructions. 3.3 Coprocessors The SA-1100 has no external coprocessor bus, so it is not possible to add external coprocessors to this device.
4 Instruction Set This section describes the instruction timing for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100). 4.1 Instruction Set The SA-1100 implements the ARM™ V4 architecture as defined in the ARM Architecture Reference, 28-July-1995, with previously noted options and additions. 4.2 Instruction Timings Table 4-1 lists the instruction timing for the SA-1100. The result delay is the number of cycles that the next sequential instruction would stall if it used the result as an input.
5 Coprocessors The operation and configuration of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) is controlled with coprocessor instructions, configuration pins, and memory-management page tables. The coprocessor 15 instructions manipulate on-chip registers that control the configuration of the cache, write buffer, MMU, read buffer, breakpoints, and other configuration options. Note: 5.
Coprocessors 5.2 Coprocessor 15 Definition The SA-1100 coprocessor 15 contains registers that control the cache, MMU, and write buffer operation as well as some clocking functions. These registers are accessed using CPRT instructions to coprocessor 15 with the processor in any privileged mode. Only some of registers 0–15 are valid; the result of an access to an invalid register is unpredictable. Table 5-1 lists the coprocessor 15 control registers. Table 5-1.
Coprocessors 5.2.2 Register 1 – Control Register 1 is a read/write register containing control bits. All writable bits in this register are forced low by reset. The shaded bits (also labeled r) are reserved and are not readable or writable.
Coprocessors 5.2.3 Register 2 – Translation Table Base Register 2 is a read/write register that holds the base of the currently active level 1 page table. Bits <13:0> are undefined on read, ignored on write. 31 14 13 0 Translation Table Base 5.2.4 Register 3 – Domain Access Control Register 3 is a read/write register that holds the current access control for domains 0 to 15.
Coprocessors 5.2.8 Register 7 – Cache Control Operations Register 7 is a write-only register. The CRm and OPC_2 fields are used to encode the cache control operations. Operation for all other values for OPC_2 and CRm is unpredictable. Function 5.2.
Coprocessors 5.2.10 Register 9 – Read-Buffer Operations The read buffer is controlled and accessed through register 9 of coprocessor 15. The functions supported are: flush-all buffers, flush-a-single entry, load-an-entry (1, 4 or 8 words), and enable/disable user mode access. The CRm and OPC_2 fields are used to encode these control operations. All other values for OPC_2 and CRm are undefined and the results of using them are unpredictable.
Coprocessors 5.2.12 Register 13 – Process ID Virtual Address Mapping The SA-1100 supports the remapping of virtual addresses through a process ID (PID) register. The 6-bit PID value is OR’ed with bits 30..25 of the virtual address when bits 31..25 of the virtual address are zero. This effectively remaps the address to one of 64 “slots” in the lower 2 Gbyte address space. The following table shows the OPC_2 and CRm field encodings used to access the process ID register.
Coprocessors 5.2.13 Register 14 – Debug Support (Breakpoints) The SA-1100 supports address and data breakpoints through register 14 of coprocessor 15. The instruction formats follow. For a description of the breakpoint operation, see Chapter 15, “Debug Support”. The following table shows the OPC_2 and CRm field encodings used to access the address and data breakpoints. Function OPC_2 CRm Access data breakpoint address register (DBAR). 0b000 0b0000 Access data breakpoint value register (DBVR).
Coprocessors 5.2.14 Register 15 – Test, Clock, and Idle Control Register 15 is a write-only register. The CRm and OPC_2 fields are used to encode the following control operations. Operation for all other values of OPC_2 and CRm is unpredictable. Function OPC_2 CRm Enable odd-word loading of the linear feedback shift register ( LFSR) 0b001 0b0001 Enable even-word loading of LFSR 0b001 0b0010 Clear LFSR 0b001 0b0100 Move LFSR to R14.
Caches, Write Buffer, and Read Buffer 6 To reduce effective memory access time, the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) has an instruction cache, a data cache, a write buffer, and a read buffer. All except the read buffer are transparent to program execution. The following sections describe each of these units and give all necessary programming information. 6.1 Instruction Cache (Icache) The SA-1100 contains a 16 Kbyte instruction cache (Icache).
Caches, Write Buffer, and Read Buffer 6.1.3 Icache Enable/Disable and Reset The Icache is automatically disabled and flushed on the assertion of nRESET. Once enabled, cacheable read accesses cause lines to be placed in the cache. If the Icache is subsequently disabled, no new lines are placed in the cache, but the cache is still searched and if the data is found, it will be used by the processor. If the data in the cache must not be used, then the cache must be flushed. 6.1.3.
Caches, Write Buffer, and Read Buffer memory-management page table. For this reason, in order to use the Dcaches, the MMU must be enabled. The two functions may be enabled simultaneously with a single write to the control register. Note: 6.2.1 The Dcaches operate with virtual addresses, so care must be taken to ensure that their contents remain consistent with the virtual-to-physical mappings performed by the memory-management unit.
Caches, Write Buffer, and Read Buffer 6.2.3 Software Dcache Flush The SA-1100 supports the flush and clean operations on single entries of the Dcaches by writes to the cache operations registers. The flush whole cache is also supported. Note that since this is a write-back cache, in order to prevent the loss of data, a flush whole must be preceded by a sequence of loads to cause the cache to write back any dirty entries.
Caches, Write Buffer, and Read Buffer 6.2.4.1 Enabling the Dcaches To enable the Dcaches, make sure that the MMU is enabled first by setting bit 0 in the control register, then enable the Dcaches by setting bit 2 in the control register. The MMU and Dcaches can be enabled simultaneously with a single control register write. 6.2.4.2 Disabling the Dcaches To disable the Dcache, clear bit 2 in the control register. 6.
Caches, Write Buffer, and Read Buffer 6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0) If the write buffer is enabled and the processor performs a write to a bufferable but noncacheable location and misses in the Dcaches, the data is placed in the write buffer and the CPU continues execution. As with the cacheable case, merging is allowed only on store multiples. The write buffer performs the external write sometime later. 6.3.2.
Caches, Write Buffer, and Read Buffer Any two data words with the same virtual address may not be contained in the RB at the same time. If an RB allocate references a data word that is already contained in another RB entry, then the old RB entry is invalidated and the new allocation is performed. It is possible for a portion of a cache clock at a given virtual address to be contained in one RB entry while another portion of the same block is contained in another RB entry.
Memory-Management Unit (MMU) 7 This chapter describes the memory-management functions. 7.1 Overview The Intel® StrongARM® SA-1100 Microprocessor (SA-1100) implements the standard ARM™ memory-management functions using two 32-entry fully associative translation buffers (TBs). One is used for instruction accesses and the other for data accesses. On a TB miss, the translation table hardware is invoked to retrieve the translation and access permission information.
Memory-Management Unit (MMU) 7.3.1 Cacheable Reads (Linefetches) A linefetch can be safely aborted on any word in the transfer. If an abort occurs during the linefetch, the cache is purged so it will not contain invalid data. If the abort happens before the word that was requested by the access is returned, the load is aborted. If the abort happens after the word that was requested by the access is returned, the load completes and the fill is aborted (but no exception is generated). 7.3.
Memory-Management Unit (MMU) Note: Care must be taken if the translated address differs from the untranslated address because the three instructions following the enabling of the MMU will have been fetched using “flat translation”, and enabling the MMU may be considered a branch with delayed execution. A similar situation occurs when the MMU is disabled.
8 Clocks This section describes the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) clocks. The following diagram shows the distribution of clocks in the SA-1100. The 3.6864-MHz oscillator feeds both PLLs. The primary PLL provides clocks for the core logic and a 7.36-MHz clock for several of the serial controllers. The core, Dcaches, and read and write buffers use either the full-speed core clock or the divided-down clock.
Clocks 8.2 Core Clock Configuration Register The core clock frequency is configured by software through the core clock configuration field (CCF<4:0>) in the power manager phase-locked loop (PLL) configuration register (PPCR). This field should be programmed during the boot sequence for the desired full-speed operation. nRESET clears the field by selecting the lowest frequency operation. See Section 9.5, “Power Manager” on page 9-26 for the physical address used to access this register.
Clocks 8.3 Driving SA-1100 Crystal Pins from an External Source In most applications, a 3.6864-MHz crystal will be connected between the PXTAL and the PEXTAL pins. Similarly, a 32.768-kHz crystal will be connected between the TXTAL and TEXTAL pins. In some applications, supplying these clocks from an external source may be preferred. This is accommodated in the SA-1100 design by: • Supplying the 32.768-kHz clock from an external source — Only the TXTAL pin is driven. The TEXTAL pin must be left floating.
Clocks If the PXTAL or TXTAL pin is driven above the voltage indicated, there will be no permanent damage to the processor for pin voltages less than 2.5 V. However, ESD diodes on these pins will attempt to clamp the voltage at approximately 1.5 V. The clamping action results in significant noise injected into an internally generated supply used by several sensitive circuits on the processor.
System Control Module 9 This chapter describes the system control module that controls several processor-wide system functions. The units contained in the system control module are: the general-purpose I/O ports, the interrupt controller, the real-time clock, the operating system timer, the power manager, and the reset controller. 9.
System Control Module Figure 9-1. General-Purpose I/O Block Diagram Pin Direction Register Alternate Function Register 0 GPIO Pin Pin Set and Clear Registers 1 Alternate Function (Output) Alternate Function (Input) Edge Detect Edge Detect Status Register Rising Edge Detect Enable Register Falling Edge Detect Enable Register Pin-Level Register 9.1.
System Control Module 9.1.1.1 GPIO Pin-Level Register (GPLR) The state of each of the GPIO port pins is visible through the GPIO pin-level register (GPLR). Each bit number corresponds to the port pin number from bit 0 to bit 27. This is a read-only register that is used to determine the current level of a particular pin (regardless of the programmed pin direction). The following table shows the locations of the 28 pin-level bits within the GPLR. This is a read-only register.
System Control Module 9.1.1.2 GPIO Pin Direction Register (GPDR) Pin direction is controlled by programming the GPIO pin direction register (GPDR). The GPDR contains one direction control bit for each of the 28 port pins. If a direction bit is programmed to a one, the port is an output. If it is programmed to a zero, it is an input. At hardware reset, all bits in this register are cleared, configuring all GPIO pins as inputs. Soft resets and sleep reset have no effect on this register.
System Control Module 9.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output Clear Register (GPCR) When a port is configured as an output, the user controls the state of the pin by writing to either the GPIO pin output set register (GPSR) or the GPIO pin output clear register (GPCR). An output pin is set by writing a one to its corresponding bit within the GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR. These are write-only registers.
System Control Module 9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and Falling-Edge Detect Register (GFER) Each GPIO port can also be programmed to detect a rising-edge, falling-edge, or either transition on a pin. When an edge is detected that matches the type of edge programmed for the pin, a status bit is set. The interrupt controller can be programmed to signal an interrupt to the CPU or wake up the SA-1100 from sleep mode when any one of these status bits is set.
System Control Module 9.1.1.5 GPIO Edge Detect Status Register (GEDR) The GPIO edge detect status register (GEDR) contains 28 status bits that correspond to the 28 GPIO port pins. When an edge detect occurs on a pin that matches the type of edge programmed in the GRER and/or GFER registers, the corresponding status bit is set in GEDR. Once a GEDR bit is set, the CPU must clear it. GEDR status bits are cleared by writing a one to them. Writing a zero to a GEDR status bit has no effect.
System Control Module 9.1.1.6 GPIO Alternate Function Register (GAFR) The GPIO alternate function register (GAFR) contains 28 control bits that correspond to the 28 GPIO port pins. When the processor sets a bit in the GAFR, the corresponding GPIO pin is switched over to that pin’s alternate function. See the following section for details on alternate functions. This register is cleared to all zeros on all reset conditions.
System Control Module 9.1.2 GPIO Alternate Functions Most GPIO pins have an alternate function that can be invoked to enable additional functionality within the SA-1100. If a GPIO is used for this alternate function, then it cannot be used as a GPIO at the same time. Pins 0 and 1 are reserved because of their special use during sleep mode and are not available for any alternate function. The following table shows each GPIO pin and its corresponding alternate function.
System Control Module 9.1.3 GPIO Register Locations The following table shows the registers associated with the GPIO block and the physical addresses used to access them.
System Control Module 9.2 Interrupt Controller The SA-1100 interrupt controller provides masking capability for all interrupt sources and combines them into their final state, either an FIQ or IRQ processor interrupt. The interrupt hierarchy of the SA-1100 is a two-level structure. The first level of the structure, represented by the interrupt controller IRQ pending register (ICIP) and the interrupt controller FIQ pending register (ICFP) contain the all-enabled and unmasked interrupt sources.
System Control Module 9.2.1.1 Interrupt Controller Pending Register (ICPR) The ICPR is a 32-bit read-only register that shows all active interrupts in the system. These bits are not affected by the state of the mask register (ICMR). The following table shows the pending interrupt source assigned to each bit position in the ICPR. Also included in the table are the source units for the interrupts and the number of second-level interrupts associated with each.
System Control Module 9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP) The ICIP and the ICFP contain one flag per interrupt (32 total) that indicates an interrupt request has been made by a unit. Inside the interrupt service routine, the ICIP and ICFP are read to determine the interrupt source. In general, software then reads status registers within the interrupting device to determine how to service the interrupt.
System Control Module 9.2.1.3 Interrupt Controller Mask Register (ICMR) The interrupt controller mask register (ICMR) contains one mask bit per pending interrupt bit (32 total). The mask bits control whether a pending interrupt bit will generate a processor interrupt (IRQ or FIQ). When a pending interrupt becomes active, it is sent to the CPU only if its corresponding ICMR mask bit is set to a one. Note that the mask bits are ignored when the SA-1100 is in idle mode.
System Control Module 9.2.1.4 Interrupt Controller Level Register (ICLR) The interrupt controller level register (ICLR) controls whether a pending interrupt generates an FIQ or an IRQ CPU interrupt. If a pending interrupt is unmasked, the corresponding ICLR bit field is decoded to select which CPU interrupt should be asserted. If the interrupt is masked, then the corresponding bit in the ICLR has no effect.
System Control Module 9.2.1.5 Interrupt Controller Control Register (ICCR) The interrupt controller control register (ICCR) contains a single control bit, the disable idle mask bit (DIM). When set, this bit inhibits the idle mode operation where the output of the ICMR is OR’ed to all ones. If this bit is set, then the interrupts that are capable of bringing the SA-1100 out of idle mode are defined by the contents of the ICMR. The following table shows the location of all interrupt level bits in the ICCR.
System Control Module 9.2.2 Interrupt Controller Register Locations The following table shows the registers associated with the interrupt controller block and the physical addresses used to access them. Address 9.
System Control Module 9.3.2 RTC Alarm Register (RTAR) The real-time clock alarm register is a 32-bit register that is readable and writable by the processor. Following each rising edge of the 1-Hz clock, this register is compared to the RCNR. If the two are equal and the enable bit is set, then the alarm bit in the RTC status register is set. The value in this register is undefined after the assertion of nRESET. 9.3.
System Control Module 9.3.4 RTC Trim Register (RTTR) The RTTR is programmed by the user to select the frequency of the 1-Hz clock. If this register is not programmed and left at its reset value (all zeros), then the 1-Hz clock will actually be running at 32.768 kHz. See the following section for details on how to calculate the value in this register. The following table shows the location of all bits in the RTTR. All reserved bits are read as zeros and are unaffected by writes. .
System Control Module 9.3.5.2 RTTR Value Calculations After the true frequency of the oscillator is known, it must be split into integer and fractional portions. The integer portion of the value (minus one) is loaded into the C0-C15 field of the RTTR. This value is compared against a 16-bit counter clocked by the output of the 32.768-kHz oscillator. The counter resets and generates a pulse when the two values are equal. This pulse constitutes the raw 1-Hz signal.
System Control Module This trim setting leaves an error of .16 cycles per 1023 seconds. The error calculation yields (in parts-per-million or ppm): 0.16 cycles 1 sec Error = --------------------------- X ------------------------------- = 0.002 ppm 1023 sec 32768 cycles Maximum Error Calculation Versus Real-Time Clock Accuracy As seen from trim example #2, the maximum possible error approaches 1 clock per 210-1 seconds.
System Control Module 9.4.1 OS Timer Count Register (OSCR) The OS timer count register is a 32-bit counter that increments on rising edges of the 3.6864-MHz clock. This counter can be read or written at any time. It is recommended that the system write-protect this register through the MMU protection mechanisms. 9.4.2 OS Timer Match Registers 0–3 (OSMR<0>, OSMR<1>, OSMR<2>, OSMR<3>) These registers are 32 bits wide and are readable and writable by the processor.
System Control Module 9.4.4 OS Timer Status Register (OSSR) This status register contains status bits indicating whether a match has occurred on any of the four match registers. These bits are set when the event occurs (following the rising edge of the 3.6864-MHz clock) and cleared by writing a one to the proper bit position. Writing zeros to this register has no effect. All reserved bits read as zeros and are unaffected by writes; a question mark indicates that the value is unknown at reset.
System Control Module 9.4.5 OS Timer Interrupt Enable Register (OIER) This register contains four enable bits indicating whether a match between one of the match registers and the OS timer counter will set a status bit in the OSSR. Each match register has a corresponding enable bit. Clearing an enable bit does not clear the corresponding interrupt status bit if that bit is already set.
System Control Module 9.4.7 OS Timer Register Locations Table 9-1 shows the registers associated with the OS timer and the physical addresses used to access them. Table 9-1.
System Control Module 9.5 Power Manager The SA-1100 contains power management logic that controls the transition between three different modes of operation: run, idle, and sleep. These modes are used to reduce processor power consumption at times when some functions are not needed, or when the system’s power supply is low or out of regulation. Each of the respective modes is associated with a reduced level of power consumption. Idle mode is entered via software.
System Control Module 9.5.2.2 Exiting Idle Mode Any enabled interrupt from the system unit or peripheral unit will cause a transition from idle mode back to run mode. Note that the interrupt controller (ICMR) mask register is ignored during idle mode, meaning that an interrupt does not need to be unmasked to bring the SA-1100 out of idle. When an interrupt occurs, the CPU clocks are reactivated, the wait for interrupt instruction is completed, and run program flow resumes.
System Control Module 9.5.3.3 The Sleep Shutdown Sequence The sleep state machine begins the shutdown sequence. This sequence consists of three steps. • In the first step, the following actions occur: a. Power manager switches the GPIO output pins to their sleep state. This sleep state is programmed in advance by loading the power manager GPIO sleep state register (PGSR) into the GPIO output data register. (See the Section 9.1, “General-Purpose I/O” on page 9-1.) b.
System Control Module • In the first step of the wake-up sequence, the following actions occur: a. The PWR_EN pin is asserted, indicating that the external supply must apply power on the VDDI pins. b. An internal timer begins to time the power ramp. This timer waits for approximately 10 ms. c. The 3.686-MHz oscillator is enabled for operation if it was originally programmed to be disabled. d.
System Control Module Also, the SA-1100 provides the power manager scratchpad register (PSPR) for saving any general processor state during sleep. This register may be written by the processor and the contents will survive sleep mode. The bits in this register are not explicitly used by the SA-1100, but may be used by software to index into ROM space to retrieve memory controller configuration, for example. Note: 9.5.3.
System Control Module Figure 9-3. Transitions Between Modes of Operation Power on, nRESET asserted HARDWARE RESET nRESET asserted nRESET asserted nRESET negated RUN Wait for interrupt instruction Force sleep bit set, or VDD or battery fault pins asserted System or peripheral unit interrupt IDLE SLEEP VDD or battery fault pins asserted CPU clock held low; all other resources active, wait for interrupt Table 9-2.
System Control Module 9.5.6 Pin Operation in Sleep Mode The SA-1100 pins are categorized by the following types based on their behavior during sleep mode: Type 1 – These pins are outputs and are driven low during sleep. These pins hold their state after sleep mode is exited until the DRAM_control_hold bit in the PSSR is cleared. Type 2 – These pins are outputs and are normally driven to a one in sleep.
System Control Module 9.5.7 Power Manager Registers The power manager is controlled through eight 32-bit registers. The power manager control register (PMCR) is used to allow software invocation of sleep mode. The sleep status register (PSSR) contains status bits that indicate why sleep mode was invoked. The power manager scratchpad register (PSPR) is a general-purpose register used to store processor data during sleep.
System Control Module 9.5.7.2 Power Manager General Configuration Register (PCFR) The PCFR contains bits used to configure various functions within the SA-1100. The OPDE bit, if set, allows the 3.6864-MHz oscillator to be disabled during sleep mode. This bit is cleared on the assertion of nRESET. The FP and FS bits control the state of the PCMCIA control pins and the static memory control pins during sleep. The following table shows the bit-field definitions for this register.
System Control Module 9.5.7.3 Power Manager PLL Configuration Register (PPCR) The PPCR contains bits used to configure the core operating frequency generated by the PLL. The following table shows the bit-field definitions for this register. See Chapter 8, “Clocks” for the frequencies generated through settings in this register. Note that the contents of this register are preserved during sleep mode and do not need to be re-initialized after a wake-up event.
System Control Module 9.5.7.4 Power Manager Wake-Up Enable Register (PWER) The following table shows the location of all wake-up interrupt enable bits in the PWER. For a GPIO to serve as a wake-up source, it must be programmed as an input in the GPDR. When a fault condition is detected in the VDD_FAULT or BATT_FAULT pins, this register is set to hexadecimal 0000 0003, enabling only GP<1,0> as wake-up sources. This register is also set to this value on hard reset (nRESET asserted).
System Control Module 9.5.7.5 Power Manager Sleep Status Register (PSSR) PSSR contains five status flags. The software sleep status flag is set when sleep mode is entered as a result of the force sleep (FS) control bit being set by the CPU. The battery fault status bit is set any time the BATT_FAULT pin is asserted (even when the SA-1100 is already in sleep mode).
System Control Module Bit 3 Name DH Description DRAM control hold. This bit is set upon exit from sleep mode and indicates that the RAS<3:0> and CAS<3:0> continue to be held low and that the DRAMs are still in self-refresh mode. This bit should be cleared by the processor (by writing a one to it) after the DRAM interface has been configured but before any DRAM access is attempted. The RAS and CAS lines are released when this bit is cleared. This bit is cleared on hardware reset.
System Control Module 9.5.7.6 Power Manager Scratch Pad Register (PSPR) The power manager also contains a 32-bit register to save processor configuration information in any format the user desires. The power manager scratch pad register (PSPR) is a holding register that is powered by the VDDx power supply pins and is never reset (only configured via writes). Any value can be written to it while in run mode. The value remains intact while in sleep mode, and can be read once sleep mode is exited.
System Control Module 9.5.7.8 Power Manager Oscillator Status Register (POSR) The power manager oscillator status register (POSR) is a single-bit, read-only register that contains a status bit indicating whether the 32.768-kHz oscillator is up to speed after a hardware reset. This bit is set after the expiration of a timer that is clocked by a ring oscillator. This bit will be set within 2–10 seconds after the negation of nRESET.
System Control Module 9.6 Reset Controller The reset controller manages the various reset sources within the SA-1100. From a programmer’s view, it is visible as two registers: one used to invoke software reset and one to read status after booting to indicate why the processor was reset. The four types of reset in the SA-1100 include: • Hardware reset Hardware reset is invoked when the nRESET pin is asserted and resets all units in the SA-1100 to a known state.
System Control Module 9.6.1 Reset Controller Registers The reset controller contains two registers, the reset controller software reset register (RSRR) and the reset controller reset status register (RCSR). 9.6.1.1 Reset Controller Software Reset Register (RSRR) The reset controller software reset register has a software reset bit, which when set, causes a reset of the SA-1100.
System Control Module 9.6.1.2 Reset Controller Status Register (RCSR) The reset controller reset status register (RCSR) is used by the CPU to determine the last cause or causes of the reset. The SA-1100 has four sources of reset: • • • • Hardware reset Software reset Watchdog reset Sleep mode reset Each RCSR status bit is set by a different source of reset, and can be cleared by writing a one back to that bit. Note that the hardware reset state of software, watchdog, and sleep mode reset bits is zero.
Memory and PCMCIA Control Module 10 The external memory bus interface for the Intel ® StrongARM® SA-1100 Microprocessor (SA-1100) supports standard fast-page and EDO asynchronous DRAMs, burst and nonburst ROMs, Flash EPROMs, SRAM, and PCMCIA expansion devices. It is programmable through the memory interface configuration registers. Figure 10-1 shows a block diagram of the maximum configuration of the memory controller. Figure 10-1.
Memory and PCMCIA Control Module 4 byte selects, nCAS<3:0>, 12 bits of multiplexed row and column addresses, nWE, and nOE. The SA-1100 performs CAS before RAS refresh (CBR) during normal operation and supports self-refreshing DRAMs during power-down sleep mode. • Static Memory Interface The static memory interface has four chip selects, nCS<3:0>, and 26 bits of byte address, A<25:0>, for access of up to 64 Mbyte of memory in each of four banks.
Memory and PCMCIA Control Module 10.1.1 Example Memory System Figure 10-2 shows a system using 1M x 16 DRAMs for a total of 16 Mbyte of DRAM. Two banks of ROM and two banks of Flash EPROM are shown, each on a 32-bitwide databus. The PCMCIA interface is not shown. Figure 10-2.
Memory and PCMCIA Control Module 10.1.2 Types of Memory Accesses The SA-1100 performs memory accesses for the following operations: Unbuffered write Level 1 translation fetch Uncached read Level 2 translation fetch Buffered write Cache line copyback Linefetch Read-lock-write sequence Read buffer fetch Internal DMA read Internal DMA write SA-1100 will only generate a subset of all possible transactions on the bus.
Memory and PCMCIA Control Module Table 10-1. SA-1100 Transactions Read single 1 Read burst 4 Description Starting Address Bits <4:2> Burst Size Bus Operation Any Generated by core, DMA, or read buffer request. 0 Generated by read buffer or DMA request. 4 Read burst 8 0 Generated by cacheline fills or read buffer request. Write single 1 Any 1..4 bytes are written as specified by the byte mask. Generated by write buffer or DMA request.
Memory and PCMCIA Control Module 10.2 Memory Configuration Registers The SA-1100 memory interface is programmed through a set of configuration registers that are described in the following sections. Table 10-2 shows the registers associated with the memory interface and the physical addresses used to access them. All addressing is little endian. These registers are readable and writable only as full words. They are grouped together within one page and thus all have the same memory protections.
Memory and PCMCIA Control Module 10.2.1 DRAM Configuration Register (MDCNFG) MDCNFG is a read/write register and contains control bits for configuring the DRAM. All DRAM banks must be implemented with the same type of DRAM devices. Question marks indicate that the values are unknown at reset. Bit 31 Read DRI14 Reset ? - ? Bit 15 Read TDL0 Reset ? Bit 3..
Memory and PCMCIA Control Module Bit Name 31..17 DRI<14:0> Description DRAM refresh interval. The number of memory clock cycles (divided by 4) between CAS before RAS (CBR) refresh cycles. One row is refreshed in each DRAM bank during each CBR refresh cycle. The value that must be loaded into this register is calculated as follows: DRI = Number of cycles/4 = ((Refresh time / rows) - (longest burst access time)) x Mem clock frequency /4.
Memory and PCMCIA Control Module 10.2.2 DRAM CAS Waveform Shift Registers (MDCAS0, MDCAS1, MDCAS2) MDCAS0, MDCAS1, and MDCAS2 are 32-bit read/write registers that contain the nCAS waveform for a full 8-beat burst read or write to asynchronous DRAM. Each bit represents one CPU cycle if MDCNFG:CDB2 is 0 and 2 CPU cycles (1 memory clock cycle) if MDCNFG:CDB2 is 1. The least significant bit of MDCAS0 goes out first and is the cycle coincident with the assertion of nRAS.
Memory and PCMCIA Control Module 10.2.3 Static Memory Control Registers (MSC1–0) MSC1 and MSC0 are read/write registers and contain control bits for configuring static memory selected by nCS<3:0>. Reset forces the values in these registers to the slowest possible nonburst ROM timing. Timing fields are specified as numbers of memory clock cycles. The memory clock cycle consists of two CPU cycles.
Memory and PCMCIA Control Module Bit 12..8 Name RDNx<4:0> Description ROM delay next access. Number of memory clock cycles (minus 1) from address to data valid for subsequent accesses of a burst ROM. For Flash and SRAM, this determines the write pulse width. One memory clock cycle is added to this value. 15..13 RRRx<2:0> ROM/SRAM recovery time. Number of memory clock cycles (divided by 2) from chip select deasserted after a read to next chip select (of a different memory bank) or nRAS asserted.
Memory and PCMCIA Control Module 10.2.4 Expansion Memory (PCMCIA) Configuration Register (MECR) MECR is a read/write register that contains control bits for configuring the timing of the PCMCIA interface. This register is unaffected by reset; question marks indicate that the values are unknown at reset. Writes to the reserved fields have no effect and reads return zeros.
Memory and PCMCIA Control Module Table 10-3. BS_xx Bit Encoding Bit 4..0 Name BS_xx Description 0b00000 – BCLK= 2 processor clocks (clk/2) 0b00001 – BCLK= 4 processor clocks 0b00010 – BCLK= 6 processor clocks .... 0b11101 – BCLK= 60 processor clocks 0b11110 – BCLK= 62 processor clocks 0b11111 – BCLK= 64 processor clocks Table 10-4. BCLK Speeds for 160-MHz Processor Core Frequency BCLK_SEL BCLK Cycle Time–ns 0b00000 – Every 2 processor clocks (clk/2). 12.5 0b00001 – Every 4 processor clocks.
Memory and PCMCIA Control Module 10.3 Dynamic Interface Operation This section describes the dynamic memory interface. 10.3.1 DRAM Overview The dynamic memory interface supports up to four banks of identical size and type dynamic memory on a 32-bit bus. Initialization software must set up the memory interface configuration registers with the DRAM size, type, number of row address bits, nCAS waveforms, and timing parameters. The SA-1100 generates accesses of 1–8 words.
Memory and PCMCIA Control Module 10.3.2 DRAM Timing The DRAM nCAS timing is generated using shift registers. The rate at which these shift registers are clocked is determined by MDCNFG:CDB2. The time at which to sample the read data is programmable to coincide with the deassertion of nCAS or up to 3 CPU cycles later. This method provides a way to take advantage of the EDO DRAMs while still supporting the fast-page-mode DRAMs.
Memory and PCMCIA Control Module Figure 10-3 shows the rate of the shift registers during DRAM nCAS timing for a single-beat transaction. Figure 10-3.
Memory and PCMCIA Control Module Figure 10-4 shows the rate of the shift registers during DRAM nCAS timing for burst-of-eight transactions. Figure 10-4.
Memory and PCMCIA Control Module 10.3.3 DRAM Refresh The SA-1100 provides support for CAS before RAS (CBR) refresh. When the DRAM interface is enabled [by setting any of MDCNFG:DE(3-0) and setting MDCNFG:DRI greater than zero], the refresh counter starts counting up every memory cycle (2 CPU cycles) from 0. When its value reaches the value in MDCNFG:DRI times 4, the memory controller is notified that a refresh cycle is due, then the counter is cleared and resumes counting.
Memory and PCMCIA Control Module The RT fields in the MSCx registers specify the type of memory (burst-of-four ROM, burst-of-eight ROM, nonburst ROM, Flash, SRAM) and the RBW fields specify the bus width for the memory space selected by nCS<3:0>. If a 16-bit bus width is specified, transactions take place across data pins D<15:0>. 10.4.1 ROM Interface Overview The SA-1100 provides programmable timing for both burst and nonburst ROMs.
Memory and PCMCIA Control Module Figure 10-6. Burst-of-Eight ROM Timing Diagram Memory Clock nCS0 A[25:5] RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDF+1.5 A[4:2] 0 1 2 3 4 5 6 7 nOE D0 D1 D2 D4 D5 Input Data Latch Input Data (2*RRR)+1 nCS1 Note: One extra CPU cycle (1/2 memory cycle) is added to the first access after nCS is asserted. In this example, MSC0:SCNFG0:RDF = 12 (decimal), RDN = 4, RRR = 2.
Memory and PCMCIA Control Module Figure 10-7. Eight Beat Burst Read from Burst-of-Four ROM Memory Clock nCS0 A[25:5] A[4] RDF+1.5 A[3:2] RDN+1 RDN+1 RDN+1 0 1 2 RDN+1 RDN+1 RDN+1 RDF+1 3 0 1 2 3 nOE D0 D1 D2 D3 D4 D5 D6 Input Data Latch Input Data (2*RRR)+1 nCS1 A4781-01 Figure 10-8. Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats Memory Clock (2*RRR)+1 RDF+1.
Memory and PCMCIA Control Module 10.4.3 SRAM Interface Overview The SA-1100 provides a 32-bit asynchronous SRAM interface that uses the nCAS pins for byte selects on both reads and writes (nCS<3:0> selects the SRAM bank, nOE is asserted on reads, and nWE is asserted on writes). Address bits A<25:2> provide addressability of up to 64 Mbyte of SRAM per bank. Because the nCAS signals are used to access SRAM, a system with both SRAM and DRAM is not supported.
Memory and PCMCIA Control Module In Figure 10-9, some of the parameters are defined as follows: tAS = Address setup to nCS = 1 CPU cycle tCES = nCS, nCAS setup to nWE = 2 memory clock cycles (4 CPU cycles) tASW = Address setup to nWE low (asserted) = 1/2 memory cycle (1 CPU cycle) [For A<25:5>, tASW=5 CPU cycles.
Memory and PCMCIA Control Module 10.4.6 FLASH EPROM Timing Diagrams and Parameters Flash reads have the same timing as nonburst ROMs as shown in the preceding figures. Figure 10-10 shows the timing for Flash writes. Figure 10-10.
Memory and PCMCIA Control Module 10.5 General Memory BUS Timing This section explains the boundary cases between DRAM, static, and refresh operations. 10.5.1 Static Access Followed by a DRAM Access With a static memory access, nWE is deasserted 1 memory clock cycle prior to the deassertion of nCS. Then memory control will wait 2*RRR memory clock cycles (or 1, whichever is greater) before the assertion of nRAS for a DRAM access.
Memory and PCMCIA Control Module 10.6 PCMCIA Overview The SA-1100 PCMCIA interface provides controls for one PCMCIA card slot with a PSKTSEL pin for support of a second slot. This 16-bit host interface supports 8- and 16-bit peripherals and handles common memory, I/O, and attribute memory accesses. The interface does not support the PCMCIA DMA protocol. The duration of each access is based on an internally generated clock that is programmed per address space in the MECR register.
Memory and PCMCIA Control Module 10.6.1 32-Bit Data Bus Operation The SA-1100 PCMCIA interface supports the use of a 32-bit data bus. Because the PCMCIA 2.0 is 8- or 16-bit only, the 32-bit operation is outside the scope of the PCMCIA specification. This 32-bit mode is intended for use as a nonstandard expansion bus for communication with customer-designed logic. The operation is fairly simple; if a word read or write is performed to PCMCIA memory space, then the entire 32-bit bus is read or written.
Memory and PCMCIA Control Module 10.6.2 External Logic for PCMCIA Implementation The SA-1100 requires external logic to complete the PCMCIA socket interface. Figure 10-12 and Figure 10-13 show general solutions for a one- and two-socket configuration. Figure 10-14 shows a solution for the voltage-control circuit. These diagrams provide the logical connections necessary for support of 3 V and 5 V PCMCIA cards as well as hot insertion capability.
Memory and PCMCIA Control Module Figure 10-12.
Memory and PCMCIA Control Module Figure 10-13. PCMCIA External Logic for a One-Socket Configuration Intel® StrongARM®* SA-1100 Socket 0 D<15:0> D<15:0> nPOE DIR OE# nPIOR nPCEx GPIO CD1# CD2# GPIO RDY/BSY# PSKTSEL NC A<25:0> nPREG nPCE<1:2> nPOE, nPWE nPIOW, nPIOR A<25:0> REG 6 nPWAIT nPIOIS16 6 CE<1:2># OE# WE# IOR# IOW# WAIT# IOIS1616# * StrongARM is a registered trademark of ARM Limited.
Memory and PCMCIA Control Module Figure 10-14. PCMCIA Voltage-Control Logic Intel® StrongARM®* SA-1100 Socket x 2 D<15:0> 2 BVD 1,2 VSS 1,2 EN# nCS<3> nOE Transparent Latch VPPEN 3VEN 5VEN Voltage-Control Circuit WR nWE * StrongARM is a registered trademark of ARM Limited. A6845-01 The PCMCIA card voltage may be controlled through a set of discrete registers mapped into a static chip select. For example, Figure 10-14 shows mapping to chip select 3. 10.6.
Memory and PCMCIA Control Module Figure 10-15.
Memory and PCMCIA Control Module Figure 10-16. PCMCIA I/O 16-Bit Access to 8-Bit Device CPU Clock Memory Clock BS_xx+1 BCLK A[25:1], nPREG, PSKTSEL BS_xx+1 2*(BS_xx+1) A[0] nPCE2 nPCE1 3*(BS_xx+1) 3*(BS_xx+1) BS_xx+2 nPIOR, nPIOW nIOIS16 nPWAIT Latch Read Data Read Data D[7:0] Low Byte Write Data D[7:0] Low Byte High Byte High Byte BS_xx = 1 A4788-01 Timing parameters are in CPU clock cycle units.
Memory and PCMCIA Control Module 10.7 Initialization of the Memory Interface On power-on reset, the dynamic memory interface is disabled and the static interface for the boot ROM, connected to nCS0, is configured for the slowest nonburst ROM/Flash EPROM. The ROM_SEL pin determines the bus size of the boot ROM (nCS0). Initialization software is responsible for setting up the memory interface configuration registers before enabling the DRAM interface by setting MDCNFG:DE3-0.
Memory and PCMCIA Control Module The following flow should be followed when coming out of reset, whether for sleep or power-up: • Read boot ROM and write to memory configuration registers, but do not enable DRAM banks. • If necessary, finish any DRAM power-up wait period (usually about 100 µs). • If coming out of sleep, see Section 9.5, “Power Manager” on page 9-26 on how to release the nCAS and nRAS pins from their self-refresh state.
Peripheral Control Module 11 This chapter describes the peripheral control units that are integrated within the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) and the DMA controller that services them. The peripheral units include one parallel data port to drive an LCD display, one synchronous serial port, and four asynchronous serial ports that implement different serial protocol standards.
Peripheral Control Module Figure 11-1. Peripheral Control Module Block Diagram ARM™* System Bus DMA Controller ARM™ Peripheral Bus LCD Controller L_PCLK L_BIAS Serial Port 0 UDC Serial Port 1 SDLC/UART Serial Port 2 ICP Serial Port 3 UART Serial Port 4 MCP/SSP UDC+ TXD1 TXD2 TXD3 TXD4 UDC- RXD1 RXD2 RXD3 SCLK * ARM is a trademark of ARM Limited. A6833-01 Table 11-1.
Peripheral Control Module Table 11-2 shows the base address for each of the peripheral control units. Table 11-2.
Peripheral Control Module 11.3 Interrupts Each peripheral unit interfaces to the interrupt controller within the system control module. The interrupt controller contains a 32-bit interrupt pending register, which when read, informs the user of all the units on the SA-1100 that are currently generating an unmasked interrupt. Once the user determines which unit is causing the interrupt, the unit’s status registers can be read to determine the exact cause of the interrupt.
Peripheral Control Module 11.4 Peripheral Pins Each peripheral has a number of dedicated pins with which to communicate to off-chip devices. The six peripherals of the SA-1100 use a total of 24 pins: the LCD uses twelve pins; serial port 4 four pins; and serial port 0 through 3 each use two pins. Many applications may not require the use of all six of the SA-1100’s peripherals.
Peripheral Control Module 11.5 Use of the GPIO Pins for Alternate Functions Each of the SA-1100’s six peripheral units has a number of dedicated pins that can be used to drive an LCD display, communicate serially with off-chip devices, or be used as general-purpose digital input/output pins.
Peripheral Control Module 11.6 DMA Controller The DMA controller consists of six independent DMA channels. Each channel can be configured to service any of the serial controllers. Two channels are required to service a full-duplex serial controller. The DMA controller is intended to relieve the processor of the interrupt overhead in servicing these ports with programmed I/O. If desired, any or all peripherals (except the UDC) may be serviced with programmed I/O instead of DMA.
Peripheral Control Module 11.6.1.1 DMA Device Address Register (DDARn) The DDARn is a 32-bit read/write register containing channel information regarding the target device. Writes to this register are blocked if the RUN bit in the DCSRn is one. The following figure shows the format for this register; question marks indicate that the values are unknown at reset. .
Peripheral Control Module The value written to the device select DS<3:0> field specifies which DMA request this channel responds to. The device datum width (DW) field value is fixed for each device type and indicates whether the device’s data port is one or two bytes wide. If the datum width is programmed incorrectly for a particular device select, then the results are unpredictable. The device burst size (BS) field value is fixed for each device type.
Peripheral Control Module Table 11-6.
Peripheral Control Module 11.6.1.2 DMA Control/Status Register (DCSRn) The DCSRn is a 32-bit read/write register that contains control and status bits for the channel. The following figure shows the format for this register; question marks indicate that the values are unknown at reset.
Peripheral Control Module The IE bit is the interrupt enable for the channel. An interrupt is generated if the DONEA, DONEB, or ERROR bits are set and the IE bit is set. The interrupt is negated when all of these status bits are cleared. The ERROR bit is set if the DMA controller is incorrectly programmed and points to reserved memory space. No error is generated for references to nonexistent external memory. If enabled, ERROR generates a channel interrupt.
Peripheral Control Module 11.6.1.5 DMA Buffer B Start Address Register (DBSBn) The DBSBn is a 32-bit read/write register that contains the starting memory address for buffer B. This register may be written only while STRTB in the DCSR is zero. 11.6.1.6 DMA Buffer B Transfer Count Register (DBTBn) The DBTBn is a 32-bit read/write register that contains the current transfer count in bytes for buffer B. This register may be written only when the STRTB bit for this channel is a zero.
Peripheral Control Module 11.6.3 DMA Register List The following table lists the registers contained within the DMA controller: Physical Address Register Name Symbol Channel 0 Registers 0h B000 0000 0h B000 0004 DMA device address register. DDAR0 DMA control/status register 0. Write ones to set. DCSR0 0h B000 0008 Write ones to clear. 0h B000 000C Read only. 0h B000 0010 DMA buffer A start address 0. DBSA0 0h B000 0014 DMA buffer A transfer count 0.
Peripheral Control Module Physical Address Register Name Symbol 0h B000 0070 DMA buffer A start address 3. DBSA3 0h B000 0074 DMA buffer A transfer count 3. DBTA3 0h B000 0078 DMA buffer B start address 3. DBSB3 0h B000 007C DMA buffer B transfer count 3. DBTB3 DMA device address register 4. DDAR4 Channel 4 Registers 0h B000 0080 0h B000 0084 DMA control/status register 4. Write ones to set. DCSR4 0h B000 0088 Write ones to clear. 0h B000 008C Read only.
Peripheral Control Module 11.7 LCD Controller The SA-1100’s LCD controller has three types of displays: Passive Color Mode Supports a total of 3375 possible colors, allowing any 256 colors to be displayed each frame. Active Color Mode Supports up to 65536 colors (16-bit). Passive Monochrome ModeSupports 15 gray-scale levels. Display sizes up to 1024 x 1024 pixels are supported.
Peripheral Control Module When the LCD controller is disabled, control of its pins is given to the peripheral pin controller (PPC) to be used as general-purpose digital input/output pins that are noninterruptible. The LCD controller’s pins include: • LDD<7:0> Data lines used to transmit either four or eight data values at a time to the LCD display.
Peripheral Control Module 11.7.1 LCD Controller Operation The LCD controller supports a variety of user-programmable options including display type and size, frame buffer, encoded pixel size, and output data width. Although all programmable combinations are possible, the selection of displays available within the market dictate which combinations of these programmable options are practical.
Peripheral Control Module Figure 11-3. Palette Buffer Format . Individual Palette Entry Bit Color Bit Mono 15 14 Unused 15 14 Unused 13 12 11 PBS* 13 10 9 8 7 6 Red (R) 12 11 10 9 PBS* 5 4 3 2 Green (G) 8 7 6 1 0 Blue (B) 5 4 Unused 3 2 1 0 Monochrome (M) *Note: Pixel bit size (PBS) is contained only within the first palette entry (palette entry 0).
Peripheral Control Module The first palette entry (palette entry 0) also contains an extra field that is used to synchronously configure the LCD controller at the beginning of each frame. Bits 12 and 13 of the first palette entry contain a field that is used to select the number of bits per pixel that is to be used in the next frame (see Figure 11-3).
Peripheral Control Module Figure 11-5. 8-Bits Per Pixel Data Memory Organization (Little Endian) Bit 7 6 5 4 8 bits/pixel Bit 3 2 1 0 Encoded Pixel Data<7:0> 31 24 23 16 15 8 7 0 Base + 0x200 Pixel 3 Pixel 2 Pixel 1 Pixel 0 Base + 0x204 Pixel 7 Pixel 6 Pixel 5 Pixel 4 .. Figure 11-6.
Peripheral Control Module In dual-panel mode, pixels are presented to two halves of the screen at the same time (upper and lower). A second DMA channel and input FIFO exist to support dual-panel operation. The DMA channels alternate service requests when filling the two input FIFOs. The palette buffer is implemented in DMA channel 1, but not channel 2; the base address points to the top of the encoded pixel values for channel 2. The DMA controller contains a base and current address pointer register.
Peripheral Control Module 11.7.1.3 Input FIFO Data from the LCD’s DMA is directed either to the palette or the input FIFO. The direction of data flow is switched whenever the LCD controller is first enabled and by each frame pulse. After the LCD controller is configured and enabled, the first 32 (4-, 12-, and 16-bits/pixel) or 512 (8-bit/pixel) bytes supplied by the DMA are sent to the palette. All subsequent encoded pixel data is sent to the FIFO.
Peripheral Control Module 11.7.1.5 Color/Gray-Scale Dithering For passive displays, entries selected from the lookup palette are sent to the color/gray-scale space/time base dither generator. Each 4-bit value is used to select one of 15 intensity levels. Note that two of the 16 dither values are identical (always high). The color/gray intensity is controlled by turning individual pixels on and off at varying periodic rates.
Peripheral Control Module 11.7.1.7 LCD Controller Pins Pixel data is removed from the bottom of the output FIFO and is driven in parallel onto the LCD’s data lines on the edge selected by the pixel clock polarity (PCP) bit. For a 4-bit wide bus, data is driven onto the LCD data lines LDD<3:0> starting with the most significant bit. For an 8-bit wide bus, data is driven onto LDD<7:0>; for a 12-bit bus GPIO<5:2> and LDD<7:0>; and for a 16-bit bus GPIO<9:2> and LDD<7:0>.
Peripheral Control Module 11.7.3 LCD Controller Control Register 0 LCD controller control register 0 (LCCR0) contains 10 bit fields that are used to control various functions within the LCD controller. 11.7.3.1 LCD Enable (LEN) The LCD enable (LEN) bit is used to enable and disable all LCD controller operation. When LEN=0, the LCD controller is disabled and control of all 12 of its pins is given to the peripheral pin controller (PPC) unit to be used as general-purpose I/O (noninterruptible).
Peripheral Control Module Table 11-8 shows the LCD data pins and GPIO pins used for each mode of operation and the ordering of pixels delivered to a screen for each mode of operation. Figure 11-8 shows the LCD data pin pixel ordering. Note that when dual-panel color operation is enabled, the user must configure GPIO pins 2 through 9 as outputs by setting bits 2..9 within the GPIO pin direction register (GPDR) and GPIO alternate function register (GAFR). See the Section 9.
Peripheral Control Module Figure 11-8.
Peripheral Control Module 11.7.3.4 LCD Disable Done Interrupt Mask (LDM) The LCD disable done interrupt mask (LDM) bit is used to mask or enable interrupt requests that are asserted after the LCD is disabled and the frame currently being output to the pins has completed. When LDM=0, the interrupt is enabled, and whenever the LCD disable done (LDD) status bit within the LCD status register (LCSR) is set (one), an interrupt request is made to the interrupt controller.
Peripheral Control Module Thus two 16-bit values are packed into each word in the frame buffer. Each 16-bit value is transferred via the DMA from off-chip memory to the input FIFO. Unlike 4- and 8-bit per pixel modes, the 16-bit value bypasses both the palette and the dither logic, and is placed directly in the output FIFO to be output on the LCD’s data pins. Increasing the size of the pixel representation allows a total of 64K colors to be generated.
Peripheral Control Module 11.7.3.8 Big/Little Endian Select (BLE) The big/little endian select (BLE) bit selects whether the LCD controller views external memory organization of the frame buffer as big or little endian. When BLE=0, little endian mode is selected and pixel data is organized within the off-chip frame buffer as shown in Figure 11-4 through Figure 11-7. Pixels are packed into words starting with the least-significant nibble, byte, or half-word.
Peripheral Control Module The following table shows the location of all 10 bit-fields located in LCD control register 0 (LCCR0). The user must program the control bits within all other control registers before setting LEN=1 (a word write can be used to configure LCCR0 while setting LEN after all other control registers have been programmed), and also must disable the LCD controller when changing the state of any control bit within the LCD controller.
Peripheral Control Module Bit 7 Name PAS Description Passive/active display select. 0 – Passive or STN display operation enabled. Dither logic is enabled. 1 – Active or TFT display operation enable. Dither logic bypassed, pin timing changes to support continuous pixel clock, output enable, VSYNC, HSYNC signals. 8 BLE Big/little endian select.
Peripheral Control Module 11.7.4 LCD Controller Control Register 1 LCD controller control register 1 (LCCR1) contains four bit fields that are used as modulus values for a collection of down counters, each of which performs a different function to control the timing of several of the LCD’s pins. 11.7.4.1 Pixels Per Line (PPL) The pixels per line (PPL) bit-field is used to specify the number of pixels in each line or row on the screen.
Peripheral Control Module 11.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW) The 8-bit beginning-of-line pixel clock wait count (BLW) field is used to specify the number of “dummy” pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the previous line has been negated, the value in BLW is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line.
Peripheral Control Module 11.7.5 LCD Controller Control Register 2 LCD controller control register 2 (LCCR2) contains four bit fields that are used as modulus values for a collection of down counters, each of which performs a different function to control the timing of several of the LCD’s pins. 11.7.5.1 Lines Per Panel (LPP) The lines per panel (LPP) bit field is used to specify the number of lines or rows present on the LCD panel being controlled.
Peripheral Control Module VSW does not affect generation of the frame clock signal in passive mode. Passive LCD displays require that the frame clock is active on the rising edge of the first line clock pulse of each frame, with adequate setup and hold time. To meet this requirement, the LCD controller’s frame clock pin is asserted on the rising edge of the first pixel clock for each frame.
Peripheral Control Module The following table shows the location of the four bit fields located in LCD control register 2 (LCCR2). The LCD controller must be disabled (LEN=0) when changing the state of any field within this register. Address: 0h B010 0024 Bit 31 30 LCCR2: LCD Controller Control Register 2 29 28 27 26 25 24 23 22 Read/Write 21 20 BFW Reset 0 - - Bit Reset 9..
Peripheral Control Module 11.7.6 LCD Controller Control Register 3 LCD controller control register 3 (LCCR3) contains seven different bit fields that are used to control various functions within the LCD controller. 11.7.6.1 Pixel Clock Divider (PCD) The 8-bit pixel clock divider (PCD) field is used to select the frequency of the pixel clock.
Peripheral Control Module 11.7.6.3 AC Bias Pin Transitions Per Interrupt (API) The 4-bit ac bias pin transitions per interrupt (API) field is used to specify the number of L_BIAS pin transitions to count before setting the ac bias count status (ACS) bit in the LCD controller status register that signals an interrupt request. After the LCD controller is enabled, the value in API is loaded to a 4-bit down counter and the counter decrements each time the ac bias pin is inverted.
Peripheral Control Module 11.7.6.7 Output Enable Polarity (OEP) The output enable polarity (OEP) bit is used to select the active and inactive states of the output enable signal in active display mode. In this mode, the ac bias pin is used as an enable that signals the off-chip device when data is actively being driven out using the pixel clock. The pixel clock continuously toggles during operation of active mode (PAS=1). When OEP=0, the L_BIAS pin is active high and inactive low.
Peripheral Control Module Bit 21 Name HSP Description Horizontal sync polarity. 0 – L_LCLK pin is active high and inactive low. 1 – L_LCLK pin is active low and inactive high. Active and passive mode: horizontal sync pulse/line clock active between lines, after end-of-line wait period. 22 PCP Pixel clock polarity. 0 – Data is driven on the LCD’s data pins on the rising edge of L_PCLK. 1 – Data is driven on the LCD’s data pins on the falling edge of L_PCLK. 23 OEP Output enable polarity.
Peripheral Control Module 11.7.8 DMA Channel 1 Base Address Register DMA channel 1 base address register (DBAR1) is a 32-bit register that is used to specify the base address of the off-chip frame buffer for DMA channel 1. The base address pointer register can be both read and written. Addresses programmed in the base address register must be aligned on quadword boundaries; the least significant four bits (DBAR1<3:0>) must always be written with zeros.
Peripheral Control Module 11.7.9 DMA Channel 1 Current Address Register DMA channel 1 current address register (DCAR1) is a 32-bit read-only register that is used by DMA channel 1 to keep track of the address of the DMA transfer currently in progress or the address of the next DMA transfer.
Peripheral Control Module 11.7.10 DMA Channel 2 Base and Current Address Registers DMA channel 2’s base and current address registers (DBAR2 and DCAR2) function exactly like DMA channel 1’s except that they are used exclusively for dual-panel operation. (See the preceding sections.) When SDS=1, DMA channel 2 is used to supply frame buffer data to the lower half of the display.
Peripheral Control Module 11.7.11 LCD Controller Status Register The LCD controller status register (LCSR) contains bits that signal overrun and underrun errors for both the input and output FIFOs, ac bias pin transition count, LCD disabled, DMA base update ready, and DMA transfer bus error conditions. Each of these hardware-detected events signal an interrupt request to the interrupt controller. Each of the LCD’s status bits signal an interrupt request as long as the bit is set.
Peripheral Control Module 11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt) The ac bias count status (ABC) bit it set each time the ac bias pin (L_BIAS) transitions a particular number of times as specified by the ac bias pin transitions per interrupt (API) field in LCCR3. If API is programmed with a nonzero value, a counter is loaded with the value in API and is decremented each time the L_BIAS pin reverses state.
Peripheral Control Module 11.7.11.10 Output FIFO Underrun Lower Panel Status (OUL) (read/write, maskable interrupt) The output FIFO underrun lower panel status (OUL) bit is set when the lower panel’s output FIFO is completely empty and the LCD’s data pin driver logic attempts to fetch data from the FIFO. It is cleared by writing a one to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0). 11.7.
Peripheral Control Module Bit 2 Name BER Description Bus error status. 0 – DMA has not attempted an access to reserved/nonexistent memory space. 1 – DMA has attempted an access to a reserved/nonexistent location in external memory. The errant DMA read returns zeros. 3 ABC AC bias count status. 0 – AC bias transition counter has not decremented to zero, or API is programmed to all zeros.
Peripheral Control Module 11.7.12 LCD Controller Register Locations Table 11-9 shows the registers associated with the LCD controller and the physical addresses used to access them. Figure 11-34 to Figure 11-38 describe the LCD controller timing parameters. Table 11-9.
Peripheral Control Module 11.7.13 LCD Controller Pin Timing Diagrams Figure 11-10. Passive Mode Beginning-of-Frame Timing VSP = 0 L_FCLK LEN set to 1 HSP = 0 L_LCLK L_PCLK VSW = 1 LDD[x:0] ELW = 2 Line 0 Data BLW = 2 Line 1 Data HSW = 6 Line 2 Data PPL = 16 Notes: LEN - LCD enable: 0 - LCD is disabled. 1 - LCD is enabled. VSP - Vertical sync polarity: 0 - Frame clock is active high, inactive low. 1 - Frame clock is active low, inactive high.
Peripheral Control Module Figure 11-11. Passive Mode End-of-Frame Timing L_FCLK L_LCLK L_PCLK ELW = 1 LDD[x:0] Line 479 Data VSW = 2 BLW = 1 Line 0 Data LPP = 480 Notes: BLW - Beginning-of-line pixel clock wait count: 0 to 256 "dummy" pixel clock periods to wait after line clock is negated before asserting pixel clocks (pixel clock does not transition).
Peripheral Control Module Figure 11-12. Passive Mode Pixel Clock and Data Pin Timing L_FCLK L_LCLK PCP = 0 L_PCLK Data Pins Sampled by the Display LDD[3:0]* Pixels 0 through 3 Pixels 4 through 7 Data Pins Change Pixels 8 through 11 Pixels 12 through 15 *DPD = 0 Notes: PCP - Pixel clock polarity: 0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge of pixel clock.
Peripheral Control Module Figure 11-13. Active Mode Timing VSP = 0 L_FCLK (VSYNC) LEN set to 1 HSW = 4 L_LCLK HSP = 0 (HSYNC) VSW = 0 L_BIAS (OE) L_PCLK BFW = 1 BFW = 2 LDD[7:0], GPIO[9:2] ELW = 1 BLW = 1 Line 0 Data Line 1 Data PPL = 16 Notes: LEN - LCD enable: 0 - LCD is disabled. 1 - LCD is enabled. VSP - Vertical sync polarity: 0 - Vertical sync clock is active high, inactive low. 1 - Vertical sync clock is active low, inactive high.
Peripheral Control Module Figure 11-14. Active Mode Pixel Clock and Data Pin Timing L_FCLK (VSYNC) L_BIAS OE) L_LCLK (HSYNC) PCP = 0 L_PCLK Data Pins Sampled by the Display LDD[7:0], GPIO[9:2] Pixels 0 through 15 Pixels 16 through 31 Data Pins Change Pixels 32 through 47 Pixels 48 through 63 Notes: PCP - Pixel clock polarity: 0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge of pixel clock.
Peripheral Control Module 11.8 Serial Port 0 – USB Device Controller This section describes the implementation-specific options of the USB protocol for a device controller as it applies to serial port 0, such as number, type, and function of the endpoints, interrupts to the CPU, transmit/receive FIFO interface, and so on. It is assumed that the user has a working knowledge of the USB standard. The UDC is USB-compliant and supports all standard device requests issued by the host.
Peripheral Control Module 11.8.1.1 Signalling Levels USB uses differential signalling to encode data and to communicate various bus conditions. The USB specification refers to the J and K data states to differentiate between high- and low-speed transmission. Because the UDC supports only 12-Mbps transmission, references are made only to actual data state 0 and actual data state 1. Four distinct states are represented using differential data by decoding the polarity of the UDC+ and UDC- pins.
Peripheral Control Module 11.8.1.2 Bit Encoding USB uses nonreturn to zero inverted (NRZI) to encode individual bits. Both the clock and the data are encoded and transmitted within the same signal. Instead of representing data by controlling the state of the signal, transitions are used. A zero is represented by a transition, and a one is represented by no transition (this produces the data).
Peripheral Control Module 11.8.1.3 Field Formats Individual bits are assembled into groups called fields. Fields are used to construct packets and packets are used to construct frames or transactions. The seven USB field types include: sync, packet identifier, address, endpoint, frame number, data, and CRC fields. A sync is preceded by the idle state on the USB bus and is always the first field of every packet. The first bit of a sync field signals the start of packet (SOP) to the UDC or host.
Peripheral Control Module 11.8.1.4 Packet Formats USB supports four packet types: token, data, handshake, and special. A token packet is placed at the beginning of a frame and is used to identify OUT, IN, SOF, and SETUP transactions. OUT and IN frames are used to transfer data, SOF packets are used to time isochronous transactions, and SETUP packets are used for control transfers to configure endpoints. A token packet consists of a sync, a PID, an address, an endpoint, and a CRC5 field (see Figure 11-16).
Peripheral Control Module 11.8.1.5 Transaction Formats Packets are assembled into groups to form transactions. Four different transaction formats are used in the USB protocol. Each is specific to a particular endpoint type: bulk, control, interrupt, and isochronous. Note that isochronous and interrupt transactions are not supported by the UDC and are not described in this section.
Peripheral Control Module Figure 11-21.
Peripheral Control Module Table 11-12 shows a summary of all device requests. Users should refer to the Universal Serial Bus Specification Revision 1.0 for a full description of host device requests. Table 11-12. Host Device Request Summary Request 11.8.2 Name SET_FEATURE Used to enable a specific feature such as device remote wake-up and endpoint stalls. CLEAR_FEATURE Used to clear or disable a specific feature. SET_CONFIGURATION Configures the UDC for operation.
Peripheral Control Module 11.8.3 UDC Control Register The UDC control register (UDCR) contains seven control bits: two to enable or disable the UDC and five to mask the transmit and receive FIFO service requests. 11.8.3.1 UDC Disable (UDD) The UDC disable (UDD) bit is used to enable and disable the UDC. When UDD=0, the UDC is enabled for serial transmission or reception. When UDC=1, it is disabled and the UDC+ and UDCpins are tristated. If UDD is written to one the entire UDC design is reset.
Peripheral Control Module 11.8.3.7 Suspend/Resume Interrupt Mask (SRM) The suspend/resume interrupt mask (SRM) bit is used to mask or enable the suspend/resume interrupt request. When SRM=1, the interrupt is masked, and the SUSIR/RESIR bits in the status/interrupt register are not allowed to be set. When SRM=0, the interrupt is enabled, and whenever a suspend or resume condition occurs, the SUSIR or RESIR bit is set.
Peripheral Control Module 11.8.4 UDC Address Register The UDC address register contains a 7-bit field that holds the device address. After a reset of the UDC core, the value of this register is zero. The CPU writes an address to this register when it receives a SET_ADDRESS from the USB host controller. It extracts the address assigned to the UDC from the SET_ADDRESS command and writes the value into the UDC address register.
Peripheral Control Module 11.8.6 UDC IN Max Packet Register The UDC IN max packet register holds the value of the number of bytes the UDC core is to transmit minus one. This is done in order to accommodate maximum packets of 256 bytes, without going to a max packet field of more than 8 bits. In order to transmit packets of 256 bytes, a value of 0xff (255) should be written into the IN max packet register.
Peripheral Control Module 11.8.7 UDC Endpoint 0 Control/Status Register The UDC endpoint zero control/status register contains 8 bits that are used to operate endpoint zero (control endpoint). 11.8.7.1 OUT Packet Ready (OPR) The OUT packet ready bit is set by the UDC when it receives a valid token to endpoint zero. When this bit is set, the EIR bit will be set in the UDC status/interrupt register if endpoint zero interrupts are enabled.
Peripheral Control Module 11.8.7.8 Serviced Setup End (SSE) The serviced setup end bit will clear the SE bit (5) when writing a one. Address: 0h 8000 0010 Bit 0 Read/Write 7 6 5 4 3 2 1 0 SSE SO SE DE FST SST IPR OPR 0 0 0 0 0 0 0 0 Reset Bit UDCCS0 Name OPR Description OUT packet ready (read-only). 1 – OUT packet ready. 1 IPR IN packet ready (read/write 1 to set). 1 – IN packet ready. 2 SST 3 FST Sent stall (read/write 1 to clear). 1 – UDC sent stall handshake.
Peripheral Control Module 11.8.8 UDC Endpoint 1 Control/Status Register The UDC endpoint 1 control/status register contains 6 bits that are used to operate endpoint 1 (OUT endpoint). 11.8.8.1 Receive FIFO Service (RFS) The receive FIFO service bit will be set if the receive FIFO has between 8 and 12 or more bytes (out of 20) in it. Because the FIFOs are asynchronous, the exact threshold cannot be determined, but is guaranteed to be in this range.
Peripheral Control Module 11.8.8.7 Bits 7..6 Reserved Bits 7..6 are reserved for future use. Address: 0h 8000 0014 Bit 7 6 Res. Reset Bit 0 0 UDCCS1 Read/Write 5 4 3 2 1 0 RNE FST SST RPE RPC RFS 0 0 0 0 0 0 Name Description Receive FIFO service (read-only). 0 RFS 0 – Receive FIFO has less than 12 bytes. 1 – Receive FIFO has 12 bytes or more. Receive packet complete (read/write 1 to clear). 1 RPC 0 – Error/status bits invalid.
Peripheral Control Module 11.8.9 UDC Endpoint 2 Control/Status Register The UDC endpoint 2 control status register contains 6 bits that are used to operate endpoint 2 (IN endpoint). 11.8.9.1 Transmit FIFO Service (TFS) The transmit FIFO service bit will be active if there are 8 or less (out of 16) bytes remaining in the transmit FIFO. This bit will be used as a DMA request to trigger the DMA unit to service the transmit FIFO. 11.8.9.
Peripheral Control Module 11.8.9.7 Bits 7..6 Reserved Bits 7..6 are reserved for future use. Address: 0h 8000 0018 Bit 7 6 Res. Reset Bit 0 0 0 UDCCS2 5 4 3 2 1 0 FST SST TUR TPE TPC TFS 0 0 0 0 0 0 Name TFS Read/Write Description Transmit FIFO service (read-only). 0 – Transmit FIFO has more than 8 bytes. 1 – Transmit FIFO has 8 bytes or less. 1 TPC Transmit packet complete (read/write 1 to clear). 0 – Error/status bits invalid.
Peripheral Control Module 11.8.10 UDC Endpoint 0 Data Register The UDC endpoint 0 data register is actually an 8-bit x 8-entry bidirectional FIFO. When the host transmits data to the UDC endpoint 0, the CPU reads the UDC endpoint 0 register to access the data. When the UDC is sending data to the host, the CPU writes the data to be sent into the UDC endpoint 0 register.
Peripheral Control Module 11.8.12 UDC Data Register The UDC data register (UDDR) is an 8-bit register corresponding to both the top and bottom entries of the transmit and receive FIFOs, respectively. Data is placed by the UDC’s receive logic into the top of the receive FIFO. The data is transferred down the FIFO to the lowest location that is empty. When UDDR is read, the bottom entry of the 8-bit receive FIFO is accessed.
Peripheral Control Module 11.8.13 UDC Status/Interrupt Register The UDC status/interrupt register (UDCSR) contains bits that are used to generate the UDC’s interrupt request. Each bit in the UDC status/interrupt register is logically ORed together to produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC status/interrupt register to determine why the interrupt occurred. Every bit in the UDCSR is controlled by a mask bit in the UDC control register.
Peripheral Control Module 11.8.13.6 Reset Interrupt Request (RSTIR) The reset interrupt request register will be set if the REM bit in the UDC control register is cleared and the host issues a reset. When the host issues a reset, the entire UDC is reset. The RSTIR bit retains its state so software can determine that the design was reset. Address: 0h 8000 0030 Bit 7 6 Res.
Peripheral Control Module 11.8.14 UDC Register Locations Table 11-13 shows the registers associated with the UDC and the physical addresses used to access them. Table 11-13. UDC Control, Data, and Status Register Locations Address 11.
Peripheral Control Module Used as a UART, serial port 1 is identical to serial port 3. It supports most of the functionality of the 16C550 protocol including 7 and 8 bits of data (odd, even, or no parity), one start bit, either one or two stop bits, and transmits a continuous break signal.
Peripheral Control Module Figure 11-22. FM0/NRZ Bit Encoding Example (0100 1011) Bit Value LSB 1 1 0 1 0 0 1 MSB 0 NRZ Data FM0 Data 11.9.1.2 Frame Format SDLC uses a flag (reserved bit pattern) to denote the beginning of a frame of information and to synchronize frame transmission. The flag contains eight bits that start and end with a zero, and contains six sequential ones in the middle (01111110).
Peripheral Control Module 11.9.1.5 Data Field The data field can be any length that is a multiple of 8 bits, including zero. The user determines the data field length according to the application requirements and transmission characteristics of the target system. Usually a length is selected that maximizes the amount of data that can be transmitted per frame to allow the CRC checker to consistently detect all errors during transmission.
Peripheral Control Module 11.9.1.8 Receive Operation Once the SDLC receiver is enabled, it enters hunt mode, searching the incoming data stream for the flag (01111110). The flag serves to achieve bit synchronization, denotes the beginning of a frame, and delineates the boundaries of individual bytes of data. The end of the flag denotes the beginning of the address byte. Once the flag is found, the receiver is synchronized to incoming data and hunt mode is exited.
Peripheral Control Module If the user disables the receiver during operation, reception of the current data byte is stopped immediately, the serial shifter and receive FIFO are cleared, control of the RXD1 pin is given to the peripheral pin control (PPC) unit, and all clocks used by the receive logic are automatically shut off to conserve power. However, the transmitter continues to function as normal. 11.9.1.
Peripheral Control Module 11.9.1.11 Transmit and Receive FIFOs To reduce chip size and power consumption, the SDLC’s FIFOs use self-timed logic (they are not clocked). Because of process and environmental variations, the depth at which a service request is triggered to empty the receive FIFO is variable. This variation spans a maximum of four FIFO entries; the receive FIFO service request can be made at four different FIFO depths.
Peripheral Control Module The status registers contain bits that signal CRC, overrun, underrun, and receiver abort errors, and the transmit FIFO service request, receive FIFO service request, and end-of-frame conditions. Each of these hardware-detected events signals an interrupt request to the interrupt controller. The status registers also contains flags for transmitter busy, receiver synchronized, receive FIFO not empty, transmit FIFO not full, and receive transition detect (no interrupt generated).
Peripheral Control Module 11.9.3.4 Bit Modulation Select (BMS) The bit modulation select (BMS) bit selects whether the SDLC uses NRZ or FM0 bit encoding for both transmit and receive data. When BMS=0, FM0 encoding is selected and when BMS=1, NRZ encoding is selected. In frequency modulation zero (FM0) encoding, a transition occurs on every bit boundary.
Peripheral Control Module 11.9.3.7 Receive Clock Edge Select (RCE) When sample clock operation is enabled (SCE=1), the receive clock edge select (RCE) bit is used to select which edge of the clock input from or output to GPIO pin 16 to use (rising or falling) to synchronously sample data from the receive pin. When RCE=0, each bit received is sampled on the rising edge of the sample clock; when RCE=1, bits are sampled on the clock’s falling edge.
Peripheral Control Module 4 SCE Sample clock enable. 0 – On-chip baud rate generator and digital PLL used to transmit and receive SDLC data. 1 – A clock is input or output via GPIO pin 16 and is used to synchronously sample receive data and drive transmit data. Note: BMS must be programmed to select NRZ encoding when sample clock operation is enabled (BMS=1). 5 SCD Sample clock direction. 0 – If sample clock enabled, it is input using GPIO pin 16.
Peripheral Control Module 11.9.4.2 Transmit Enable (TXE) The transmit enable (TXE) bit is used to enable and disable SDLC transmit operation. When TXE=0, the transmit logic is disabled and its clocks are turned off to conserve power. When TXE=1, the SDLC transmitter logic is enabled for serial transmission. It is required that the user first program all other control bits before setting TXE.
Peripheral Control Module 11.9.4.6 Address Match Enable (AME) The address match enable (AME) bit is used to enable or disable the receive logic from comparing the address programmed in the address match value (AMV) bit field to the address of all incoming frames. When AME=1, data is stored in the receive FIFO for only those frames that have addresses that match AMV, and for any frame that contains an address that contains all ones (11111111), denoting a global address.
Peripheral Control Module The following table shows the location of the bits within SDLC control register 1. RXE and TXE are the only control bits in this register that are reset to a known state to ensure the SDLC is disabled following a reset of the SA-1100. The reset state of all other control bits is unknown (indicated by question marks) and must be initialized before enabling the SDLC.
Peripheral Control Module 11.9.5 SDLC Control Register 2 SDLC control register 2 (SDCR2) contains the 8-bit address match value field that is used by the SDLC to selectively receive frames. 11.9.5.1 Address Match Value (AMV) The 8-bit address match value (AMV) field is programmed with an address value that is used to selectively store only the data within receive frames that have the same address value. The address match enable (AME) bit must be set to enable this function.
Peripheral Control Module 11.9.6 SDLC Control Registers 3 and 4 SDLC control register 3 (SDCR3) contains the upper 4 bits and SDLC control register 4 (SDCR4) the lower 8 bits of the baud rate divisor field. 11.9.6.1 Baud Rate Divisor (BRD) The 12-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the SDLC. A total of 4096 different baud rates can be selected, ranging from a minimum of 56.24 bps to a maximum of 230.4 Kbps. The baud rate generator uses the 3.
Peripheral Control Module 11.9.7 SDLC Data Register The SDLC data register (SDDR) is an 8-bit register corresponding to both the top and bottom entries of the transmit and receive FIFOs, respectively. When SDDR is read, the lower 8 bits of the bottom entry of the 11-bit receive FIFO is accessed. As data enters the top of the receive FIFO, bits 8..10 are used as tags to indicate various conditions that occur during reception of each piece of data.
Peripheral Control Module The following table shows the bit locations corresponding to the data field and end-of-frame bit as well as the cyclic redundancy check and receiver overrun error bits within the SDLC data register. Note that both FIFOs are cleared when the SA-1100 is reset, the transmit FIFO is cleared when writing TXE=0, and the receive FIFO is cleared when writing RXE=0.
Peripheral Control Module 11.9.8 SDLC Status Register 0 SDLC status register 0 (SDSR0) contains bits that signal the transmit FIFO service request, receive FIFO service request, receiver abort, transmit FIFO underrun, and the end/error in receive FIFO condition. Each of these hardware-detected events signal an interrupt request to the interrupt controller. A bit that can cause an interrupt signals the interrupt request as long as the bit is set. Once the bit is cleared, the interrupt is cleared.
Peripheral Control Module which indicates that the address, control, and data fields did not add up to an even multiple of 8 bits. When an abort is received, the current data byte within the serial shifter is discarded, the least recent byte (the oldest of the two bytes) of data in the temporary FIFO is moved to the receive FIFO (the other byte is discarded), and the EOF tag is set in the FIFO entry that corresponds to the last piece of data that was received before the frame was aborted.
Peripheral Control Module The following table shows the bit locations corresponding to the status and flag bits within SDLC status register 0. Note that the reset state of all writable status bits is unknown (indicated by question marks) and must be cleared (by writing a one to them) before enabling the SDLC. Also note that writes to reserved bits are ignored and reads return zeros.
Peripheral Control Module 11.9.9 SDLC Status Register 1 SDLC status register 1 (SDSR1) contains flags and status bits that indicate when the receiver is synchronized, the transmitter is active, that the transmit FIFO is not full, that the receive FIFO is not empty, a transition has been detected on the receive line, and when an end of frame, CRC error, or underrun error has occurred. All bits within SDSR1 are noninterruptible. 11.9.9.
Peripheral Control Module register. After the error in FIFO (EIF) status bit is set, the user should always read SDSR1 first to check EOF before reading the data value from SDDR because EOF corresponds to the current data byte at the bottom of the receive FIFO and is updated each time data is removed from the FIFO. 11.9.9.
Peripheral Control Module The following table shows the location of the flag and status bits within SDLC status register 1. The bits within this register do not produce interrupt requests. Note that the reset value of RTD is unknown (indicated by question marks) and must be cleared if set following a reset of the SA-1100. The remainder of SDSR1 is read-only (writes are ignored). .
Peripheral Control Module 11.9.10 UART Register Locations Table 11-14 shows the registers associated with the UART and the physical addresses used to access them. See the Section 11.9, “Serial Port 1 – SDLC/UART” on page 11-78 for a description of the programming and operation of the UART (serial port 1’s UART is identical to serial port 3’s UART). Table 11-14.
Peripheral Control Module 11.9.11 SDLC Register Locations Table 11-15 shows the registers associated with the SDLC and the physical addresses used to access them. Table 11-15.
Peripheral Control Module 11.10.1 Low-Speed ICP Operation Following reset, both the UART and HSSP are disabled, which causes the peripheral pin controller (PPC) to assume control of the port’s pins. Reset causes the PPC to configure all of the peripheral pins as inputs, including serial port 2’s transmit (TXD2) and receive (RXD2) pins. Reset also causes the UART’s transmit and receive FIFOs to be flushed (all entries invalidated).
Peripheral Control Module Figure 11-25. UART Frame Format for IrDA Transmission (<= 115.2 Kbps) Start Bit Data<7> Data<6> Data<5> Data<4> Data<3> Data<2> Data<1> Data<0> Stop Bit UTCR0-2 Programming: 11.10.
Peripheral Control Module Figure 11-27. 4PPM Modulation Example Nibble 3 Nibble 2 Nibble 1 Nibble 0 Original Byte Order 1 0 1 1 0 0 0 1 Reordered Nibbles 0 1 0 0 1 1 1 0 Nibble 0 Chips Nibble 1 1 Nibble 2 Nibble 3 3 2 4 Timeslots 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 125ns 4PPM Data Receive data sample counter frequency = 6X pulse width; each timeslot sampled on third clock. 11.10.2.
Peripheral Control Module 11.10.2.3 Address Field The 8-bit address field is used by a transmitter to target a select group of receivers when multiple stations are connected to the same set of serial lines. The address allows up to 255 stations to be uniquely addressed (00000000 to 11111110). The global address (11111111) is used to broadcast messages to all stations.
Peripheral Control Module 11.10.2.7 Baud Rate Generation The baud rate is derived by dividing down a fixed 48-MHz clock generated by one of the two on-chip PLLs by six. The 8-MHz baud (or timeslot) clock for the receive logic is synchronized with the 4PPM data stream each time a transition is detected on the receive data line using a digital PLL. To encode a 4-Mbps data stream, the required “chip” frequency is 2.0 MHz, with four timeslots per chip at a frequency of 8.0 MHz.
Peripheral Control Module When the receive FIFO is one- to two-thirds full, an interrupt or DMA transfer is signalled. If the data is not removed soon enough and the FIFO is completely filled, an overrun error is signalled when the receive logic attempts to place additional data into the full FIFO. Once the FIFO is full, all subsequent data bytes received are lost while all FIFO contents remain intact.
Peripheral Control Module At the end of each frame transmitted, the HSSP outputs a pulse called the serial infrared interaction pulse (SIP). A SIP is required at least every 500 ms to keep slower speed devices (115.2 Kbps and slower) from colliding with the higher speed transmission. The SIP simulates a start bit that causes all low-speed devices to stay off the bus for at least another 500 ms. Transmission of the SIP pulse causes the TXD2 pin to be forced high for a duration of 1.625 µs and low for 7.
Peripheral Control Module operations. All reads and writes of the ICP by the CPU should be wordwide. Two separate, dedicated DMA requests exist for both the transmit and the receive FIFOs. If the DMA controller is used to service the transmit and/or receive FIFOs, the user must ensure the DMA is properly configured to perform bytewide accesses, using 8 bytes per burst for the HSSP and 4 bytes per burst for the UART.
Peripheral Control Module Bit 0 Name HSE Description HP-SIR enable. 0 – HP-SIR modulation disabled; ICP functions as normal UART if ITR=0. 1 – HP-SIR modulation enabled; ICP functions as low-speed IrDA port if ITR=0. 1 LPM Low-power mode. 0 – Each zero encoded as a pulse that is 3/16 of the programmed bit time if ITR=0. 1 – Each zero encoded as a pulse that is 1.6 µs wide if ITR=0. 7..2 11.10.5 — Reserved.
Peripheral Control Module 11.10.6.3 Transmit FIFO Underrun Select (TUS) The transmit FIFO underrun select (TUS) bit is used both to select what action to take as a result of a transmit FIFO underrun as well as mask or enable the transmit FIFO underrun interrupt. When TUS=0, transmit FIFO underruns are used to signal the transmit logic that the end of the frame has been reached.
Peripheral Control Module transmitting and receiving data at the same time; both are fully independent units. This function is particularly useful when using the HSSP in loopback mode. See the Section 11.10.6.2, “Loopback Mode (LBM)” on page 11-112. 11.10.6.5 Receive Enable (RXE) The receive enable (RXE) bit is used to enable or disable HSSP receive operation. When RXE=0, the receive logic is disabled and its clocks are turned off to conserve power.
Peripheral Control Module The following table shows the location of the bits within HSSP control register 0. RXE and TXE are the only control bits that are reset to a known state to ensure the HSSP is disabled following a reset of the SA-1100. The reset state of all other control bits is unknown (indicated by question marks) and must be initialized before enabling the HSSP.
Peripheral Control Module 11.10.7 HSSP Control Register 1 HSSP control register 1 (HSCR1) contains the 8-bit address match value field that is used by the HSSP to selectively receive frames. 11.10.7.1 Address Match Value (AMV) The 8-bit address match value (AMV) field is programmed with an address value that is used to selectively store only the data within receive frames that have the same address value. The address match enable (AME) bit must be set to enable this function.
Peripheral Control Module 11.10.8 HSSP Control Register 2 The HSSP control register 2 (HSCR2) contains two bit-fields that control the polarity of the transmit and receive data pins. Note that unlike the rest of the HSSP’s registers, its bits are located in byte 2 of the addressed word (bits 23..16). Word reads or writes should be used to access this register. Also note that this register resides within the PPC’s address space. 11.10.8.
Peripheral Control Module The following table shows the location of the bits within HSSP control register 2. Both bits are set to one to ensure serial port 2’s pins default to normal “true” data operation following a reset of the SA-1100. Note that the HSSP and UART must be disabled (RXE=TXE=0) when changing the state of these bits. Also note that reads of reserved bits return zero and writes have no effect.
Peripheral Control Module 11.10.9 HSSP Data Register The HSSP data register (HSDR) is an 8-bit register corresponding to both the top and bottom entry of the transmit and receive FIFOs, respectively. When HSDR is read, the lower 8 bits of the bottom entry of the 11-bit receive FIFO is accessed. As data enters the top of the receive FIFO, bits 8 – 10 are used as tags to indicate various conditions that occur during reception of each piece of data.
Peripheral Control Module The following table shows the bit locations corresponding to the data field, end-of-frame bit as well as the cyclic redundancy check and receiver overrun error bits within the HSSP data register. Note that both FIFOs are cleared when the SA-1100 is reset, the transmit FIFO is cleared when TXE=0, and the receive FIFO is cleared when RXE=0.
Peripheral Control Module 11.10.10 HSSP Status Register 0 HSSP status register 0 (HSSR0) contains bits that signal the transmit FIFO service request, receive FIFO service request, receiver abort, transmit FIFO underrun, framing error, and the end/error in receive FIFO conditions. Each of these hardware-detected events signal an interrupt request to the interrupt controller. A bit that can cause an interrupt signals the interrupt request as long as the bit is set.
Peripheral Control Module 11.10.10.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt) The transmit FIFO service request flag (TFS) is a read-only bit that is set when the transmit FIFO is nearly empty and requires service to prevent an underrun. TFS is set any time the transmit FIFO has eight or fewer entries of valid data (half-full or less), and is cleared when it has nine or more entries of valid data.
Peripheral Control Module 11.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt) The framing error status (FRE) bit is set when a frame alignment error is detected by the receive logic. A frame alignment error is detected on received data when a preamble is followed by something other than another preamble or a start flag. The following table shows the bit locations corresponding to the status and flag bits within HSSP status register 0.
Peripheral Control Module 11.10.11 HSSP Status Register 1 HSSP status register 1 (HSSR1) contains flags that indicate when the receiver is synchronized, the transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and when an end-of-frame, CRC error, or underrun error has occurred. All bits within HSSR1 are read-only and noninterruptible. 11.10.11.
Peripheral Control Module 11.10.11.6 CRC Error Status (CRE) (read-only, noninterruptible) The CRC error flag (CRE) is set when the CRC value calculated by the receive logic does not match the CRC value contained within the incoming serial data stream. The receive FIFO contains three tag bits (8, 9, and 10) that are not directly readable. Whenever a CRC error is detected, the 9th bit is set within the top entry of the receive FIFO corresponding to the last byte of data within the frame.
Peripheral Control Module The following table shows the location of the flags within HSSP status register 1. The bits within this register are read-only and do not produce interrupt requests. Note that writes to bit 7 are ignored and reads return zero. Address: 0h 8004 0078 Bit Reset Bit 0 HSSR1 7 6 5 4 3 2 1 0 Res. ROR CRE EOF TNF RNE TBY RSY 0 0 0 0 1 0 0 0 Name RSY Read-Only Description Receiver synchronized flag (read-only). 0 – Receiver is in hunt more or is disabled.
Peripheral Control Module 11.10.12 UART Register Locations Table 11-16 shows the registers associated with the UART block and the physical addresses used to access them. Table 11-16.
Peripheral Control Module 11.11 Serial Port 3 - UART Serial port 3 is a general-purpose, full-duplex, universal asynchronous receiver/transmitter (UART) that supports much of the functionality of the 16550 protocol. It can operate at baud rates from 56.24 bps to 230.4 Kbps. It supports 7 or 8 bits of data (odd, even, or no parity), one start bit, either one or two stop bits, and can transmit a continuous break signal.
Peripheral Control Module 11.11.1.1 Frame Format NRZ encoding is used by the UART to represent individual bit values. A one is represented by a line transition and a zero is represented by no line transition. Figure 11-30 shows the NRZ encoding of the data byte 8b 0100 1011. Note that the byte’s LSB is transmitted first. Figure 11-30.
Peripheral Control Module The parity, framing, and overrun error bits are transferred down the receive FIFO along with the data that caused the error. Whenever any of the four bottom FIFO entries contain one or more error bits that are set, an interrupt is generated and receive FIFO DMA requests are disabled until the error is flushed from the FIFO and the status bit that signalled the interrupt is cleared.
Peripheral Control Module removed from the receive FIFO without checking if more data is available. After this point, the user must poll a set of status bits that indicates if any data remains in the receive FIFO or if space is available in the transmit FIFO before emptying or filling the FIFOs any further. 11.11.1.6 CPU and DMA Register Access Sizes Bit positioning, byte ordering, and addressing of the UART is described in terms of little endian ordering.
Peripheral Control Module The transmit logic sets or clears the parity bit to make the total number of ones transmitted (including the parity bit) match the parity type programmed using OES (if even parity is selected (OES=1) and there is an odd number of ones in the data to be transmitted, the parity bit is set). The receive data logic counts the number of ones encountered in the incoming data stream (including the parity bit), then strips the parity bit from the data.
Peripheral Control Module 11.11.3.7 Transmit Clock Edge Select (TCE) When SCE=1, the transmit clock edge select (TCE) bit is used to select which edge of the clock input from the GPIO pin to use (rising or falling) to synchronously drive data onto the transmit pin. When TCE=0, each bit transmitted is driven on the rising edge of the sample input clock; when TCE=1, bits are driven on the clock’s falling edge. Note that the internal baud rate generator is not used in this mode. TCE is ignored when SCE=0.
Peripheral Control Module 11.11.4 UART Control Registers 1 and 2 UART control register 1 (UTCR1) contains the upper 4 bits and UTCR2 the lower 8 bits of the baud rate divisor field. 11.11.4.1 Baud Rate Divisor (BRD) The 12-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the UART. A total of 4096 different baud rates can be selected, ranging from a minimum of 56.24 bps to a maximum of 230.4 Kb/ps. The baud rate generator uses the 3.
Peripheral Control Module 11.11.5 UART Control Register 3 UART control register 3 (UTCR3) contains six different bit fields that control various functions within the UART. 11.11.5.1 Receiver Enable (RXE) The receiver enable (RXE) bit is used to enable and disable all UART receive operations. When RXE=1, the UART receive logic is enabled; when RXE=0, it is disabled.
Peripheral Control Module 11.11.5.5 Transmit FIFO Interrupt Enable (TIE) The transmit FIFO interrupt enable (TIE) bit is used to mask or enable the transmit FIFO service request interrupt. When TIE=0, the interrupt is masked and the state of the transmit FIFO service request (TFS) bit is ignored by the interrupt controller. When TIE=1, the interrupt is enabled, and whenever TFS is set (one), an interrupt request is made to the interrupt controller.
Peripheral Control Module 11.11.6 UART Data Register The UART data register (UTDR) is an 8-bit register corresponding to both the top and bottom entries of the transmit and receive FIFOs, respectively. When UTDR is read, the lower 8 bits of the bottom entry of the 10-bit receive FIFO are accessed. As data enters the top of the receive FIFO, bits 8..10 are used to indicate various error conditions that occur during reception of each piece of data.
Peripheral Control Module The following table shows the bit locations corresponding to the data field, parity, framing, and receiver overrun error bits within the UART data register. Note that both FIFOs are cleared when the SA-1100 is reset, the transmit FIFO is cleared when writing TXE=0, and the receive FIFO is cleared when writing RXE=0.
Peripheral Control Module 11.11.7 UART Status Register 0 UART status register 0 (UTSR0) contains bits that signal the transmit FIFO interrupt request, receive FIFO interrupt request, receiver idle detect, the begin and end of receiver break detect conditions, and the error in receive FIFO condition. Each of these hardware-detected events signals an interrupt request to the interrupt controller. Interruptible status bits signal an interrupt requested as long as the bit is set.
Peripheral Control Module 11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt) The receiver idle status bit (RID) is set when the receiver is enabled (RXE=1), the receive FIFO is not empty (contains at least one entry of data), and three frame periods elapse without any data having being received. When RID is set, an interrupt request is made unless the receive FIFO interrupt request mask (RIE) bit is cleared. 11.11.7.
Peripheral Control Module The following table shows the bit locations corresponding to the status bits within UART status register 0. Note that the reset state of all writable status bits is unknown (indicated by question marks) and must be cleared (by writing a one to them) before enabling the UART. Also note that writes to reserved bits are ignored and reads return zeros. .
Peripheral Control Module 11.11.8 UART Status Register 1 UART status register 1 (UTSR1) contains flags that indicate when the UART is actively transmitting characters, that the transmit FIFO is not full, that the receive FIFO is not empty, and when parity, framing, overrun, and underrun errors have occurred. All bits within UTSR1 are read-only and are noninterruptible. 11.11.8.
Peripheral Control Module 11.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible) The framing error status bit (FRE) is set when the stop bit within a frame of incoming serial data is a zero instead of a one. The receive FIFO contains three bits (8, 9, and 10) that are not directly readable. The 9th bit in the FIFO is set at the top of the FIFO whenever a byte of data that incurs a framing error is moved from the receive serial shifter to the top of the receive FIFO.
Peripheral Control Module The following table shows the bit locations corresponding to the flag bits within UART status register 1. Note that these flags do not generate interrupts, all bits are read-only, writes are ignored, and reads of reserved bits return zeros. Address: 0h 8005 0020 Bit 7 6 Reserved Reset Bit 0 0 0 UTSR1 5 4 3 2 1 0 ROR FRE PRE TNF RNE TBY 0 0 0 1 0 0 Name TBY Read-Only Description Transmitter busy flag (read-only).
Peripheral Control Module 11.11.9 UART Register Locations Table 11-18 shows the registers associated with serial port 3 and the physical addresses used to access them. Table 11-18.
Peripheral Control Module Both the MCP and the off-chip codec contain programmable 7-bit divisors, one each for the telecom and audio data. These values are used to divide the bit clock to generate a desired sampling frequency. When the codec is enabled, the divisor pairs are synchronously transferred to their respective modulus registers within the MCP and off-chip codec, and decrement using the bit clock.
Peripheral Control Module 11.12.1.1 Frame Format Each MCP data frame is 128 bits long and is divided into two subframes: 0 and 1. Subframe 0 is used by the MCP to communicate data to and from the UCB1100 or UCB1200. Subframe 1 is not used by the MCP because it is typically used to interface to high-performance stereo codecs such as Crystal’s CS4216/18.
Peripheral Control Module Note that the transmit line is pulled low any time data is not being driven onto the pin. The UCB1100 and UCB1200 have a programming option that allows them to either tristate or drive the receive line low when data is not being driven onto RXD4. As shown in Figure 11-32, MCP frames occur back-to-back. The SFRM pin is pulsed high during the last clock (128th) of the frame to indicate the start of a new frame the following SCLK period.
Peripheral Control Module If the input portion of the audio codec is enabled, when the counter reaches zero, a sample and A-to-D conversion is made and the converted value is placed within the correct field of the codec’s serial shift register for transmission back to the MCP in the next data frame. If the output portion of the audio codec is enabled, an audio data value is taken from the received data supplied by the MCP and is used for a D-to-A conversion.
Peripheral Control Module The width of each entry within the audio and telecom FIFOs is 16 bits. However, the audio codec’s sample/conversion data size is 12 bits and the telecom is 14 bits. Conversions and samples are left justified within the 16-bit audio and telecom data fields in the MCP frame as well as within the transmit and receive FIFOs. Figure 11-34 shows the required data alignment for the transmit and receive audio and telecom FIFOs.
Peripheral Control Module A register read is performed by writing a value to MCP data register 2 that contains the address of the register and the read/write bit set to a zero. Again, the data is transferred to the serial shifter on the next rising edge of the SFRM signal and is transmitted to the UCB1100 or UCB1200 during subframe 0.
Peripheral Control Module 11.12.2 MCP Register Definitions There are six registers within the MCP: two control registers, three data registers, and one status register. The control register is used to program the audio and telecom sample rates, to mask or unmask interrupt requests to service the MCP’s FIFOs, to select whether an on-chip or off-chip clock is used to drive the bit rate, and to enable/disable operation.
Peripheral Control Module Once enabled, the MCP’s audio sample rate clock decrements at the programmed frequency with a 50% duty cycle. The action outlined in the above first bullet item causes the MCP’s audio transmit FIFO logic to transfer the next available value to the audio data field within the serial shifter.
Peripheral Control Module 11.12.3.3 Multimedia Communications Port Enable (MCE) The MCP enable (MCE) bit is used to enable and disable all MCP operation. Since the MCP and SSP both share the same pins, only one can be enabled at a time. If the user enables both at the same time, the MCP has precedence and the SSP remains disabled. However, both can be enabled when the SSP pin reassignment (SPR) bit within the PPC unit is set, which assigns the SSP to GPIO pins.
Peripheral Control Module MCP within a receive data frame, the data valid bit is reset to zero for subsequent data frames until a new A-to-D sample is triggered and transmitted to the MCP. In this mode, the user should program ADM=0. In the other mode, the data valid bit is set once when the first A-to-D conversion is made and is placed in the receive data frame. However, the data valid bit remains set and the MCP cannot determine when new A-to-D conversions are available within the incoming frame.
Peripheral Control Module 11.12.3.10 Loopback Mode (LBM) The loopback mode (LBM) bit is used to enable and disable the ability of the MCP’s transmit and receive logic to communicate. When LBM=0, the MCP operates normally. The transmit and receive data paths are independent and communicate via their respective pins.
Peripheral Control Module Bit 16 Name MCE Description Multimedia communications port enable. 0 – MCP operation disabled, control of the TXD4, RXD4, SCLK, and SFRM pins given to the PPC to be used as general-purpose I/O pins. 1 – MCP operation enabled. Note that the MCP has precedence over the SSP, if MCE=1; SSE is ignored unless the SPR bit is set within the PPC, which allows the SSP to use GPIO pins while the MCP uses serial port 4’s pin for transmission. 17 ECS External clock select.
Peripheral Control Module 11.12.4 MCP Control Register 1 The MCP control register 1 (MCCR1) contains one bit that selects one of two fixed frequencies to drive the MCP. Note that this register resides within the PPC’s address space. 11.12.4.1 Clock Frequency Select (CFS) When the on-chip clock is enabled (ECS=0), the clock frequency select (CFS) bit is used to select either a 9.585-MHz or an 11.981-MHz clock to drive the MCP’s serial clock rate. When ECS=0 and CFS=0, the on-chip 3.
Peripheral Control Module 11.12.5.1 MCP Data Register 0 When MCP data register 0 (MCDR0) is read, the bottom entry of audio receive FIFO is accessed. As data is removed by the MCP’s receive logic from the incoming data frame, it is placed into the top entry of the audio receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the FIFO. Data is removed by reading MCDR, which accesses the bottom entry of the audio FIFO.
Peripheral Control Module 11.12.5.2 MCP Data Register 1 When MCP data register 1 (MCDR1) is read, the bottom entry of the telecom receive FIFO is accessed. As data is removed by the MCP’s receive logic from the incoming data frame, it is placed into the top entry of the telecom receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the FIFO. Data is removed by reading MCDR1, which accesses the bottom entry of the telecom FIFO.
Peripheral Control Module 11.12.5.3 MCP Data Register 2 MCDR2 contains 21 bits and is used to perform reads and writes to any of the UCB1100’s or UCB1200’s registers. MCDR2 contains three separate fields: MCDR2<15:0> is the 16-bit register data field, MCDR2<16> is a 1-bit read/write control bit, and MCDR2<20:17> is the 4-bit register address field.
Peripheral Control Module The following table shows the location of MCP data register 2. Note that the reset state of all MCDR2 bits is unknown (indicated by question marks), writes to reserved bits are ignored, and reads return zeros. .
Peripheral Control Module 11.12.6 MCP Status Register The MCP status register (MCSR) contains bits that signal FIFO overrun and underrun errors, and FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller. The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty, when a codec control register read or write is complete, and when the audio or telecom portion of the codec is enabled (no interrupt generated).
Peripheral Control Module 11.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt) The telecom transmit FIFO service request flag (TTS) is a read-only bit that is set when the telecom transmit FIFO is nearly empty and requires service to prevent an underrun. TTS is set whenever the telecom transmit FIFO has four or fewer entries of valid data (half-full or less), and is cleared when it has five or more entries of valid data.
Peripheral Control Module 11.12.6.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, nonmaskable interrupt) The telecom transmit FIFO underrun status bit (TTU) is set when the telecom transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the telecom transmit logic continuously transmits the last valid telecom value, which was transmitted before the underrun occurred.
Peripheral Control Module 11.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, noninterruptible) The telecom receive FIFO not empty flag (TNE) is a read-only bit that is set whenever the telecom receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any valid data.
Peripheral Control Module The following table shows the bit locations corresponding to the status and flag bits within the MCP status register. MCSR contains a collection of read/write, read-only, interruptible, and noninterruptible bits (refer to the bit descriptions above). Writes to read-only bits have no effect. The user must clear set status bits before enabling the MCP. Note that writes to reserved bits are ignored and reads return zeros; question marks indicate that the values are unknown at reset.
Peripheral Control Module Bit 6 Name TTU Description Telecom transmit FIFO underrun. 0 – Telecom transmit FIFO has not experienced an underrun. 1 – Telecom transmit logic attempted to fetch data from transmit FIFO while it was empty, request interrupt. 7 TRO Telecom receive FIFO overrun. 0 – Telecom receive FIFO has not experienced an overrun. 1 – Telecom receive logic attempted to place data into receive FIFO while it was full, request interrupt. 8 ANF Audio transmit FIFO not full (read-only).
Peripheral Control Module 11.12.7 SSP Operation Following reset, both the MCP and SSP logic within serial port 4 is disabled and control of its pins is given to the PPC that configures all four pins as inputs. To enable SSP operation, the programmer should first clear any interruptible status bits, which are set following the reset by writing a one to them.
Peripheral Control Module Figure 11-35 shows the Texas Instruments* synchronous serial frame format for a single transmitted frame and when back-to-back frames are transmitted. In this mode, SCLK and SFRM are forced low, and the transmit data line SA-1100. Once the bottom entry of the transmit FIFO contains data, SFRM is pulsed high for one SCLK period and the value to be transmitted is transferred from the transmit FIFO to the transmit logic’s serial shift register.
Peripheral Control Module Figure 11-36 shows one of the four possible configurations for the Motorola* SPI frame format for a single transmitted frame and when back-to-back frames are transmitted. In this mode, SCLK and the transmit data line (TXD4) are forced low and SFRM is forced high, whenever the SSP is disabled or the SA-1100 is reset. Once the bottom entry of the transmit FIFO contains data, SFRM is pulled low and remains low for the duration of the frame’s transmission.
Peripheral Control Module Figure 11-37 shows the National Microwire* frame format for a single transmitted frame and when back-to-back frames are transmitted. Microwire format is very similar to SPI format, except that transmission is half- instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device. During this transmit, no incoming data is received by the SSP.
Peripheral Control Module 11.12.7.2 Baud Rate Generation The baud or bit rate is derived by dividing down the 3.6864-MHz clock generated by the on-chip PLL. The clock is first divided by a fixed value of 2 and then by a programmable number between 1 and 256. This programmability provides a range of transmission rates ranging from 7.2 Kbps to 1.8432 Mbps. The resultant clock is used to drive the SCLK pin and by the transmit and receive logic’s serial shifters to drive and latch data, respectively. 11.12.
Peripheral Control Module 11.12.7.4 CPU and DMA Register Access Sizes Bit positioning, byte ordering, and addressing of the SSP are described in terms of little endian ordering. All SSP registers are 16-bits wide and are located in the least significant half-word of individual words. The ARM peripheral bus does not support byte or half-word operations. All reads and writes of the SSP by the CPU should be word wide. Two separate dedicated DMA requests exist for both the transmit and the receive FIFO.
Peripheral Control Module 11.12.9.1 Data Size Select (DSS) The 4-bit data size select (DSS) field is used to select the size of the data transmitted and received by the SSP. Data can be 4 to 16 bits in length. When data is programmed to be less than 16 bits, received data is automatically right justified and the upper bits in the receive FIFO are zero filled by the receive logic.
Peripheral Control Module 11.12.9.4 Serial Clock Rate (SCR) The 8-bit serial clock rate (SCR) bit field is used to select the baud or bit rate of the SSP. A total of 256 different bit rates can be selected, ranging from a minimum of 7.2 Kbps to a maximum of 1.8432 Mbps. The serial clock generator uses the 3.6864-MHz clock produced by the on-chip PLL, divided by a fixed value of 2, and then the programmable SCR value to generate the serial clock (SCLK).
Peripheral Control Module 11.12.10 SSP Control Register 1 The SSP control register 1 (SSCR1) contains six different bit fields that control various functions within the SSP. 11.12.10.1 Receive FIFO Interrupt Enable (RIE) The receive FIFO interrupt enable (RIE) bit is used to mask or enable the receive FIFO service request interrupt. When RIE=0, the interrupt is masked and the state of the receive FIFO service request (RFS) bit within the SSP status register is ignored by the interrupt controller.
Peripheral Control Module 11.12.10.5 Serial Clock Phase (SPH) The serial clock phase (SPH) bit selects the phase relationship of the serial clock (SCLK) signal with the serial frame (SFRM) signal when Motorola* SPI format is selected (FRF=00). When SPH=0, SCLK remains in its inactive state (as programmed by SPO) for one full SCLK period duration after SFRM is asserted (driven low).
Peripheral Control Module 11.12.10.6 External Clock Select (ECS) The external clock select (ECS) bit selects whether the on-chip 3.6864-MHz clock is used by the SSP or if an off-chip clock is supplied via GPIO pin 19. When ECS=0, the SSP uses the on-chip 3.6864-MHz clock to produce a range of serial transmission rates ranging from 7.2 Kbps to a maximum of 1.8432 Mbps. When ECS=1, the SSP uses GPIO<19> to input a clock supplied from off-chip. The frequency of the off-chip clock can be any value up to 3.
Peripheral Control Module 11.12.11 SSP Data Register The SSP data register (SSDR) is 16 bits wide and corresponds to the top and bottom entries of the transmit and receive FIFOs, respectively. When SSDR is read, the bottom entry of receive FIFO is accessed. As data is removed by the SSP’s receive logic from the incoming data frame, it is placed into the top entry of the receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the FIFO.
Peripheral Control Module 11.12.12 SSP Status Register The SSP status register (SSSR) contains bits that signal overrun errors as well as the transmit and receive FIFO service requests. Each of these hardware-detected events signals an interrupt request to the interrupt controller. The status register also contains flags that indicate when the SSP is actively transmitting characters, when the transmit FIFO is not full, and when the receive FIFO is not empty (no interrupt generated).
Peripheral Control Module 11.12.12.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt) The receive FIFO service request flag (RFS) is a read-only bit that is set when the receive FIFO is nearly filled and requires service to prevent an overrun. RFS is set whenever the receive FIFO has four or more entries of valid data (half-full or more), and is cleared when it has three or fewer (less than half-full) entries of data.
Peripheral Control Module 11.12.13 MCP Register Locations Table 11-19 shows the registers associated with the MCP and the physical addresses used to access them. Table 11-19.
Peripheral Control Module 11.13 Peripheral Pin Controller (PPC) The peripheral pin controller (PPC) takes individual control of the LCD’s and serial port 1..4’s pins when one or more of the units are disabled, allowing the user to utilize them as general-purpose digital I/O pins to communicate to off-chip resources. When controlled by the PPC, peripheral control module (PCM) pins operate similarly to GPIO pins except that they cannot perform edge detection and interrupt generation.
Peripheral Control Module Serial port 1 and serial port 4 both contain two serial-to-parallel engines that operate independently. However, because each port contains only one set of serial pins, the user can assign these pins to only one of the two protocols at a time. To allow the user to utilize both protocols, the PPC can assign one of its two serial-to-parallel engines to the pins that are dedicated to the port, and the other to a set of GPIO pins. Serial port 1 contains an SDLC and a UART.
Peripheral Control Module Bit 7..0 8 Name Description LDD<7:0 > LCD data pin direction. L_PCLK LCD pixel clock pin direction. 0 – If LCD controller disabled, LCD data pin configured as general-purpose input. 1 – If LCD controller disabled, LCD data pin configured as general-purpose output. 0 – If LCD controller disabled, LCD pixel clock pin configured as general-purpose input. 1 – If LCD controller disabled, LCD pixel clock pin configured as general-purpose output.
Peripheral Control Module 11.13.4 PPC Pin State Register Pin state is both monitored and controlled by reading/writing the PPC pin state register (PPSR). The PPSR contains 1 state bit for each of the 22 peripheral pins. This register may be read at any time to determine the current state of all peripheral pins, even when pins are controlled by the peripheral rather than the PPC.
Peripheral Control Module Bit 7..0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 31..22 11-188 Name LDD<7:0 > Description LCD data pin state. L_PCLK Read – Current state of LCD data pin returned. Write – If LCD disabled and pin configured as an output, drive value to LCD data pin. LCD pixel clock pin state. L_LCLK Read – Current state of LCD pixel clock pin returned. Write – If LCD disabled and pin configured as an output, drive value to LCD pixel clock pin. LCD line clock pin state.
Peripheral Control Module 11.13.5 PPC Pin Assignment Register The UART in serial port 1 and the SSP in serial port 4 can be reassigned to GPIO pins using the PPC pin assignment register (PPAR). The PPAR contains two bits that control the reassignment of each serial engine to an individual set of GPIO pins. 11.13.5.1 UART Pin Reassignment (UPR) The UART pin reassignment (UPR) bit is used to select whether serial port 1’s UART is assigned to GPIO pins 14 and 15.
Peripheral Control Module 11.13.6 PPC Sleep Mode Pin Direction Register When sleep mode is entered, reset is asserted to all of the SA-1100’s peripherals and to the PPC unit. The PPC pin direction register is cleared during a hard, soft, or sleep reset, causing the peripheral pins under the PPC’s control to be configured as inputs. If this register were also used to determine pin direction during sleep, the pins would all be configured as inputs.
Peripheral Control Module Bit 7..0 8 Name LDD<7:0 > L_PCLK Description LCD data sleep mode pin direction. 0 – LCD data pin configured as output and is driven low during sleep. 1 – LCD data pin configured as input during sleep. LCD pixel clock sleep mode pin direction. 0 – LCD pixel clock pin configured as output and is driven low during sleep. 1 – LCD pixel clock pin configured as input during sleep. 9 L_LCLK LCD line clock sleep mode pin direction.
Peripheral Control Module 11.13.7 PPC Pin Flag Register The PPC pin flag register (PPFR) is used to determine which peripherals are currently under the control of the PPC unit. The eight read-only flags denote whether or not each of the peripherals (except serial port 0) is enabled or is disabled and being controlled by the PPC. Note that serial ports 1..3 contain individual enables for their transmit and receive serial engines. Thus, separate flag bits exist for their transmit and receive pins.
Peripheral Control Module 11.13.8 PPC Register Locations Table 11-21 shows the registers associated with the PPC and the physical addresses used to access them. Note that serial port 2 (ICP) has implemented HSSP control register 2 and serial port 4 (MCP) has also implemented MCP control register 1 within the PPC’s address space at 0h 9006 0028 and 0h 9006 0030 respectively.
12 DC Parameters This chapter defines the dc parameters for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100). 12.1 Absolute Maximum Ratings Table 12-1 lists the absolute maximum ratings for the SA-1100. Table 12-1. SA-1100 DC Maximum Ratings Symbol Parameter VDD Core supply voltage VDDX I/O voltage Vip Voltage applied to any pin Min VSS – 0.5 MIN(VSS – 0.05, VDD – 0.3) VSS – 0.5 Max Units Note VSS + 2.1 V 1 VSS + 3.6 V 1 VSS + 3.
DC Parameters 12.2 DC Operating Conditions Table 12-2 lists the functional operating dc parameters for the SA-1100. Table 12-2. SA-1100 DC Operating Conditions Symbol Parameter Min Nom Max Units Notes Vihc† IC input high voltage 0.8 × VDDX — VDDX V 1, 2 Vilc† IC input low voltage 0.0 — 0.2 × VDDX V 1, 2 Vohc OCZ output high voltage 0.8 × VDDX — VDDX V 1, 3 Volc OCZ output low voltage 0.0 — 0.
DC Parameters 12.3 Power Supply Voltages and Currents Table 12-3 specifies the power supply voltages and currents for the SA-1100. For power supply voltages and currents for 2.0-V devices, contact the Intel Massachusetts Customer Technology Center. . Table 12-3.
13 AC Parameters This chapter defines the ac parameters for the Intel® StrongARM® SA-1100 Microprocessor (SA-1100). 13.1 Test Conditions The AC timing diagrams presented in this chapter assume that the outputs of SA-1100 have been loaded with a 50-pF capacitive load on output signals. The output pads of SA-1100 are CMOS drivers that exhibit a propagation delay that increases with the increase in load capacitance.
AC Parameters 13.2 Module Considerations The edge rates for the SA-1100 processor are such that the lumped load model presented above can only be used for etch lengths up to one inch. Over one inch of etch, the signal is a transmission line and needs to be modeled as such. 13.3 Memory Bus and PCMCIA Signal Timings During production test, the SA-1100 is placed in testclock bypass mode by the assertion of the TCKBYP pin. This mode (not intended for use by customers) bypasses the 3.
AC Parameters 13.4 LCD Controller Signals Figure 13-2 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK). Figure 13-2. LCD AC Timing Definitions L_PCLK Tpclkdv L_LDD[7:0] (rise) Tpclkdv L_LDD[7:0] (fall) L_LCLK L_BIAS L_FCLK Tpclklv Tpclkbv Tpclkfv A4775-01 13.5 MCP Signals Figure 13-3 describes the MCP timing parameters. The MCP pin timing specifications are referenced to SCLK_C. Figure 13-3.
AC Parameters 13.6 Timing Parameters Table 13-2 lists the ac timing parameters for the SA-1100 for AA and BA parts. For timing parameters for 2.0-V devices, contact the Intel Massachusetts Customer Technology Center. Table 13-2.
AC Parameters 13.6.1 Asynchronous Signal Timing Descriptions nPWAIT is an input and is received through a synchronizer. As such, it has no setup and hold specification. The user must adhere to the protocol definition. When the peripheral pins are in GPIO mode, they are read or written under software control. As outputs, they are driven valid on the pin approximately 20 ns after they are written by software.
14 Package and Pinout 14.1 Mechanical Data and Packaging Information Figure 14-1 shows the SA-1100 208-pin LQFP mechanical drawing. All measurements are in millimeters. Table 14-1 lists the SA-1100 pins in numeric order, showing the signal type for each pin. Figure 14-1. Quad Flat Pack – 1.4mm (LQFP) 30.00 View from above 28.00 Pin 208 Pin 157 Pin 1 Pin 156 30.00 28.00 SA-1100 Pin 105 Pin 52 Pin 53 Pin 104 0.50 typ 1.40 1.60 max 0.60 typ 0.22 .
Package and Pinout Table 14-1.
Mini-Ball Grid Array – (mBGA) 14.2 D C 8 7 DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM – C – // THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION !. 2. PRIMARY DATUM – C – AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. NOTES: 1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M —1982. 3.
Package and Pinout Table 14-2.
Debug Support 15 Due to the integration level of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100), many functions are not directly visible on the external pins. Therefore, some basic debug facilities are provided that are not present on the Intel® StrongARM® SA-110 Microprocessor (SA-110). These facilities are in the form of breakpoints that provide the user with the ability to stop execution after seeing a specific reference in either the instruction or data streams.
16 Boundary-Scan Test Interface The boundary-scan interface conforms to the IEEE Std. 1149.1 – 1990, Standard Test Access Port and Boundary-Scan Architecture. (Refer to this standard for an explanation of the terms used in this section and for a description of the TAP controller states.) The Intel® StrongARM® SA-1100 Microprocessor (SA-1100) supports only JTAG continuity testing. 16.
Boundary-Scan Test Interface 16.2 Reset The boundary-scan interface includes a state-machine controller (the TAP controller). In order to force the TAP controller into the correct state after power-up of the device, a reset pulse must be applied to the nTRST pin. If the boundary-scan interface is to be used, then nTRST must be driven low, and then high again. If the boundary-scan interface is not to be used, then the nTRST pin may be tied permanently low.
Boundary-Scan Test Interface 16.5.1 EXTEST (00000) The boundary-scan (BS) register is placed in test mode by the EXTEST instruction. The EXTEST instruction connects the BS register between TDI and TDO. When the instruction register is loaded with the EXTEST instruction, all the boundary-scan cells are placed in their test mode of operation. In the CAPTURE-DR state, inputs from the system pins and outputs from the boundary-scan output cells to the system pins are captured by the boundary-scan cells.
Boundary-Scan Test Interface 16.5.4 HIGHZ (00101) The HIGHZ instruction connects a 1-bit shift register (the BYPASS register) between TDI and TDO. When the HIGHZ instruction is loaded into the instruction register, all outputs are placed in an inactive drive state. In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle.
Boundary-Scan Test Interface 16.6 Test Data Registers Figure 16-2 illustrates the structure of the boundary-scan logic. Figure 16-2. Boundary-Scan Block Diagram BSINENCELL Intel® StrongARM® SA-1100 BSINCELL BSINCELL I/O Cell BSOUTCELL Core Logic BSOUTNENCELL BSOUTCELL Device ID Register Bypass Register TDO Instruction Decoder TDI Instruction Register TMS TCK TAP Controller nTDOEN nTRST * StrongARM is a registered trademark of ARM Limited. A6839-01 16.6.
Boundary-Scan Test Interface 16.6.2 SA-1100 Device Identification (ID) Code Register Purpose: This register is used to read the 32-bit device identification code. No programmable supplementary identification code is provided. Length: 32 bits Operating Mode: When the IDCODE instruction is current, the ID register is selected as the serial path between TDI and TDO.
Boundary-Scan Test Interface 16.7 Boundary-Scan Interface Signals Figure 16-3.
Boundary-Scan Test Interface Figure 16-4. Boundary-Scan Tristate Timing tck tdo Tbsoe Tbsoz Tbsde Tbsdz Data Out A4773-01 Figure 16-5.
Boundary-Scan Test Interface Table 16-1 shows the SA-1100 boundary-scan interface timing specifications. Table 16-1.
Register Summary A This appendix describes all of the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) internal registers. Physical Address Symbol Register Name 0h 9004 0000 GPLR GPIO pin level register. 0h 9004 0004 GPDR GPIO pin direction register. 0h 9004 0008 GPSR GPIO pin output set register. 0h 9004 000C GPCR GPIO pin output clear register. 0h 9004 0010 GRER GPIO rising-edge register. 0h 9004 0014 GFER GPIO falling-edge register.
Register Summary Physical Address Symbol Register Name PMCR Power manager control register. Power Manager Registers 0h 9002 0000 0h 9002 0004 PSSR Power manager sleep status register. 0h 9002 0008 PSPR Power manager scratchpad register. 0h 9002 000C PWER Power manager wakeup enable register. 0h 9002 0010 PCFR Power manager configuration register. 0h 9002 0014 PPCR Power manager PLL configuration register. 0h 9002 0018 PGSR Power manager GPIO sleep state register.
Register Summary Physical Address Symbol Register Name 0h B000 0044 DCSR2 DMA control/status register 2 – write ones to set. 0h B000 0048 Write ones to clear. 0h B000 004C Read only. 0h B000 0050 DBSA2 DMA buffer A start address 2. 0h B000 0054 DBTA2 DMA buffer A transfer count 2. 0h B000 0058 DBSB2 DMA buffer B start address 2. 0h B000 005C DBTB2 DMA buffer B transfer count 2. 0h B000 0060 DDAR3 DMA device address register 3.
Register Summary Physical Address Symbol Register Name 0hB010 0000 LCCR0 LCD controller control register 0. 0hB010 0004 LCSR LCD controller status register. 0hB010 0008 – 0hB010 000C — Reserved. 0hB010 0010 DBAR1 DMA channel 1 base address register. 0hB010 0014 DCAR1 DMA channel 1 current address register. 0hB010 0018 DBAR2 DMA channel 2 base address register. 0hB010 001C DCAR2 DMA channel 2 current address register. 0hB010 0020 LCCR1 LCD controller control register 1.
Register Summary Physical Address Symbol Register Name 0h 8002 0060 SDCR0 SDLC control register 0. 0h 8002 0064 SDCR1 SDLC control register 1. 0h 8002 0068 SDCR2 SDLC control register 2. 0h 8002 006C SDCR3 SDLC control register 3. 0h 8002 0070 SDCR4 SDLC control register 4. SDLC Registers (Serial Port 1) 0h 8002 0074 — Reserved. 0h 8002 0078 SDDR SDLC data register. 0h 8002 007C — Reserved. 0h 8002 0080 SDSR0 SDLC status register 0.
Register Summary Physical Address Symbol Register Name 0h 8005 0000 UTCR0 UART control register 0. 0h 8005 0004 UTCR1 UART control register 1. 0h 8005 0008 UTCR2 UART control register 2. 0h 8005 000C UTCR3 UART control register 3. 0h 8005 0010 — Reserved. 0h 8005 0014 UTDR UART data register. 0h 8005 0018 — Reserved. 0h 8005 001C UTSR0 UART status register 0. 0h 8005 0020 UTSR1 UART status register 1. 0h 8005 0024 – 0h 8005 FFFF — Reserved.
3.6864–MHz Oscillator Specifications B A 3.6864-MHz crystal oscillator is integrated on the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) for use as a reference frequency for the PLLs that generate the internal clocks to the processor. The phase noise of this reference frequency should be minimized because it could be amplified by the PLLs, resulting in PLL output frequency jitter.
3.6864–MHz Oscillator Specifications approximately twice the values given, the startup time in this situation will be about double the specified startup time and the current consumption will increase. Capacitances larger than twice the specified values may prevent the oscillator from starting. B.1.1.1. Parasitic Capacitance Off-chip Between PXTAL and PEXTAL The parasitic capacitance off-chip between PXTAL and PEXTAL is the board capacitance between the PXTAL and PEXTAL pins. B.1.1.2.
3.6864–MHz Oscillator Specifications B.1.2 Quartz Crystal Specification The following specifications for the quartz crystal are shown in the figure and table below. Resonance frequency (fs): Resonance frequency of the crystal. Motional capacitance (Cm): Equivalent serial capacitance in the crystal model. Motional inductance (Lm): Not generally given in supplier specification. Motional resistance (Rm): Equivalent serial resistance in the crystal model.
32.768–kHz Oscillator Specifications C A 32.768-kHz crystal oscillator is integrated on the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) for use as a time base for the real-time clock (RTC). The output frequency of the crystal oscillator is divided by 32768 (215) to deliver a 1-Hz signal to the RTC. A digital tuning circuit is included on the SA-1100 in order to calibrate the 1-Hz output for each crystal and circuit based on a set of values stored in an external EEPROM.
32.768–kHz Oscillator Specifications approximately twice the values given; the startup time in this situation will be about double the specified startup time and the current consumption will increase. Capacitances larger than twice the specified values may prevent the oscillator from starting. C.1.1.4.
32.768–kHz Oscillator Specifications Parasitic capacitance off-chip between TXTAL or TEXTAL and VSS C.1.2 — — 2 pF Parasitic resistance between TXTAL or TEXTAL to VSS 10 — — MΩ Parasitic resistance between TXTAL and TEXTAL 10 — — MΩ Quartz Crystal Specification The following specifications for the quartz crystal are shown in the figure and table below. Resonance frequency (fs): Resonance frequency of the crystal.
32.768–kHz Oscillator Specifications Load capacitance (CL) 10 Drive level — Crystal type Tuning fork (X+5o 12.5 25 pF — 1 µW or X+2o cut) The following values are not required for the crystal oscillator to function, but they directly affect the performance of the oscillator in the system because they determine the accuracy of the crystal itself. The values given represent those seen on typical crystals used for timekeeping, and are provided for information only.
Internal Test Internal Test D The Test Unit contains a register that enables certain test modes. Some of these test modes are reserved for manufacturing test and should not be invoked by an end user. D.1 Test Unit Control Register (TUCR) The Test Unit Control Register (TUCR) contains control bits that put the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) in various test modes.
Internal Test Bit D-2 Name Description 27..28 Reserved — 29..31 TSEL2-0 Test selects. Routes internal signals out onto GPIO<27> for observing internal clock signals. To observe these clocks, set bit 27 to one in the GAFR and GPDR registers and set the TSEL bits to the following settings to select which clock is driven onto GP<27>: TSEL2 TSEL1 TSEL0 GP<27>(alternate function) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 32-kHz oscillator 3.
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