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Intel

Server Board S5500WB

Technical Product Specification

Intel order number E53971-004

Revision 1.3

August 2009

Enterprise Platforms and Services Division

Summary of content (116 pages)

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Intel® Server Board S5500WB Technical Product Specification Intel order number E53971-004 Revision 1.
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Revision History Intel® Server Board S5500WB TPS Revision History Date ii 03/30/2009 Revision Number 1.0 Modifications Initial Release 04/29/2009 1.1 Formatting corrections 05/20/2009 1.2 Updated heatsink installation steps Corrected processor fault table Added jumper location figure 08/03/2009 1.3 Updated memory support Corrected PCIe slot speed Removed S4 support Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Board S5500WB TPS Table of Contents 1. 2. 3. Introduction .......................................................................................................................... 1 1.1 Section Outline ........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 Server Board Overview ......................
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Intel® Server Board S5500WB TPS Table of Contents 3.7.1 Serial ATA Support ................................................................................................ 29 3.7.2 USB 2.0 Support.................................................................................................... 29 3.8 Network Interface Controller (NIC) ........................................................................ 30 3.8.1 MAC Address Definition............................................................
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Table of Contents 5.5.1 Wake On LAN (WOL) ............................................................................................ 42 5.5.2 PCI Express* Power management ........................................................................ 43 5.5.3 PMBus*.................................................................................................................. 43 5.6 5.6.1 6. 7. SMBUS Architecture Block ..................................................................................
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Intel® Server Board S5500WB TPS 7.4.6 Serial Port Connectors........................................................................................... 65 7.4.7 USB Connectors .................................................................................................... 65 7.5 8. 9. Table of Contents Fan Headers .......................................................................................................... 66 Intel Light-Guided Diagnostics...........................................
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Table of Contents Intel® Server Board S5500WB TPS 11.3.2 ICES-003 (Canada) ............................................................................................... 86 11.3.3 Europe (CE Declaration of Conformity) ................................................................. 87 11.3.4 BSMI (Taiwan) ....................................................................................................... 87 11.3.5 KCC (Korea) ....................................................................
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Intel® Server Board S5500WB TPS List of Figures List of Figures Figure 1. Intel® Server Board S5500WB 12V................................................................................ 4 Figure 2. Intel Server Board S5500WB SSI.................................................................................. 5 Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown) .......................... 6 Figure 4. Rear Panel Connector Placement: .......................................................
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List of Figures Intel® Server Board S5500WB TPS Figure 32. Power Distribution Diagram ...................................................................................... 82 Figure 33. Diagnostic LED Placement Diagram ........................................................................ 88 x Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS List of Tables List of Tables Table 1. Intel® Server Board S5500WB Feature Set ................................................................... 2 Table 2. Intel® Server Board S5500WB System Interconnects.................................................... 7 Table 3. Intel® Server Board S5500WB Features ....................................................................... 13 Table 4. Mixed Processor Configurations ........................................................
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List of Tables Intel® Server Board S5500WB TPS Table 30. IPMB Header 4-pin (J1B2)......................................................................................... 54 Table 31. SGPIO Header (J1B1) ................................................................................................ 54 Table 32. Front Panel SSI Standard 24-pin Connector Pin-out (J1E1) ..................................... 54 Table 33. Power LED Indicator States..............................................................
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Intel® Server Board S5500WB TPS List of Tables Revision 1.
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Intel® Server Board S5500WB TPS 1. Introduction Introduction The Intel® Server Board S5500WB is a dual socket server using the Intel® Xeon® Processor 5500 series processor, in combination with the IOH and ICH10R to provide a balanced feature set between technology leadership and cost. 1.1 Section Outline This document is divided into the following chapters: • • • • • • • • • • • • • 1.
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Server Board Overview 2. Intel® Server Board S5500WB TPS Server Board Overview The Intel® Server Board S5500WB is a monolithic printed circuit board (PCB) with features designed to support the Internet Portal Data Center markets. The following table provides a high-level product feature list. Table 1.
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Intel® Server Board S5500WB TPS Feature Power Connections Server Board Overview Description SSI SKU One SSI-EEB compliant 24-pin main power connector (SSI only SKU) One SSI compliant 8-pin CPU power connector One SSI compliant 5-pin power control Connector (SSI only SKU) 12-V Only SKU One 8-pin power connector One 6-pin Aux power connector for 3.
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Server Board Overview 2.1 Intel® Server Board S5500WB TPS Intel® Server Board S5500WB Server Board The Intel® Server Board S5500WB has two board SKUs. An SSI-compliant and a 12-V only SKU. The board layouts of the SKUs are shown. Figure 1. Intel® Server Board S5500WB 12V 4 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 2. Intel Server Board S5500WB SSI Revision 1.
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Server Board Overview 2.2 Intel® Server Board S5500WB TPS Server Board Connector and Component Layout A B C D E F G H PP OO NN MM I LL J K KK JJ II HH GG L BB EE CC Z FF DD AA Y W X V U T S Q O M R P N AF003051 Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown) 6 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview Table 2.
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Server Board Overview 2.2.1 Intel® Server Board S5500WB TPS Board Rear Connector Placement ® The Intel Server Board S5500WB has the following board rear connector placement: C D E F G A B H AF003052 Figure 4. Rear Panel Connector Placement: Description ID LED B Status LED F RJ-45 Serial port connector C RJ-45 GbE/Dual USB connector G DB15 Video D Dual USB connector H Diagnostic LEDs 2.2.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 5. Baseboard and Mounting holes Revision 1.
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Server Board Overview Intel® Server Board S5500WB TPS Figure 6. Connector Locations 10 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 7. Primary Side Height Restrictions Revision 1.
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Server Board Overview Intel® Server Board S5500WB TPS Figure 8. Secondary Side Height Restrictions 12 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS 3. Functional Architecture Functional Architecture The Intel® Server Board S5500WB is a purpose build, power-optimized server used in a 1U rack. Memory and processor socket placement is made to minimize the amount of fan power required to cool these components. Voltage Regulators (VRDs) are optimized for a particular range of memory and CPU power that suits the target Internet Portal Datacenter (IPDC) segment of the market.
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Functional Architecture 3.
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Intel® Server Board S5500WB TPS 3.3 Functional Architecture Intel® Xeon® 5500 Series The Intel® 5500 series processors are the first-generation server/workstation processor to implement the following key new technologies: • Intel® QuickPath Memory Controller • Point-to-point link interface based on the Intel® QuickPath Interconnect (Intel® QPI), which was formerly known as the Common System Interface (CSI).
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Functional Architecture • Intel® Server Board S5500WB TPS Major: If the Post Error Pause setup option is enabled, the system goes directly to the error manager. Otherwise, the system continues to boot and no prompt is given for the error. The error is logged to the error manager. Table 4. Mixed Processor Configurations Error Severity Processor family not identical Fatal System Action The BIOS detects the error condition and responds as follows: • Logs the error into the system event log (SEL).
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Intel® Server Board S5500WB TPS Error Processor Intel® QuickPath Interconnect speeds not identical Functional Architecture Severity Halt System Action The BIOS detects the error condition and responds as follows: • Adjusts all processor interconnect frequencies to lowest common denominator. • Logs the error into the SEL. • Alerts the Integrated BMC about the configuration error. • Does not disable the processor. • Displays “0195: Processor 0x Intel(R) QPI speed mismatch” message in the Error Manager.
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Functional Architecture Intel® Server Board S5500WB TPS C Pin 1 D AF003060 . Figure 11. Removing the socket cover 7. Remove the protective socket cover. (See letter “D” in Figure 11) 8. Align the pins of the processor with the socket and insert the processor into the socket. Orientation Notch AF003061 Figure 12. Installing processor 9. Lower the load plate and load lever of the ILM cover completely. NOTE: Make sure the alignment triangle mark and the alignment triangle cutout align correctly.
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Intel® Server Board S5500WB TPS Functional Architecture posts to physically prevent mis-orientation of the package. These orientation features also provide an initial rough alignment of the package to the socket. C. The socket has alignment walls at the four corners to provide final alignment of the package. Figure 13. Package Installation/Remove Feature 3.3.3.2 Installing the Processor Heatsink(s) CAUTION: The heatsink has Thermal Interface Material (TIM) located on the bottom of it.
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Functional Architecture Intel® Server Board S5500WB TPS Figure 14. Installing/Removing Heatsink 3.3.3.3 Removing the Processor Heatsink To remove the heatsink, follow these steps: 1. Loosen the four captive screws on the heatsink corners in a diagonal manner according to the numbers shown in Figure 1 as follows: a) Starting with the screw at location 1, loosen it by giving it two rotations in the anticlockwise direction and stop. (IMPORTANT: Do not fully loosen.
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Intel® Server Board S5500WB TPS Functional Architecture PCI Express*, PCI-X*, PCI (including peer-to-peer communication support), AGP (Accelerated Graphics Port), and so forth, through the appropriate bridges. Each Intel® QPI link consists of 20 pairs of uni-directional differential lanes for the transmitter and receiver plus a differential forwarded clock.
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Functional Architecture Intel® Server Board S5500WB TPS The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies. Memory modules of mixed speed are supported by automatic selection of the highest common frequency of all memory modules.
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Intel® Server Board S5500WB TPS 3.4.3 Functional Architecture ECC Support If at least one non-ECC DIMM is present in the system, the system reverts to non-ECC mode. UDIMMs can be ECC or non-ECC; RDIMMs are always ECC enabled. Non-ECC DIMMs are not validated and not recommended for server use. 3.4.4 Memory Reservation for Memory-mapped Functions A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset, processor, and BIOS (flash) memory-mapped I/O regions.
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Functional Architecture 3.4.7 Intel® Server Board S5500WB TPS Installing and Removing Memory The silkscreen on the board next to CPU1 displays: DIMM_A2, DIMM_A1, DIMM_B1, DIMM_C1, and next to CPU2 display: DIMM_D2, DIMM_D1, DIMM_E1, DIMM_F1 starting from the inside of the board. DIMM_A1 is the blue socket closest to the CPU 1 socket. For memory channel A, the server board requires DDR3 DIMMs within a channel to be populated starting with the DIMM farthest from the processor.
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Intel® Server Board S5500WB TPS Functional Architecture 3.4.7.2 Removing DIMMs To remove a DIMM, follow these steps: 1. 2. 3. 4. 5. Turn off all peripheral devices connected to the server. Turn off the server. Remove the AC power cord from the server. Remove the server’s cover. Gently spread the retaining clips at each end of the socket. The DIMM lifts from the socket. 6. Holding the DIMM by the edges, lift it from the socket and store it in an anti-static package. 7.
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Functional Architecture Intel® Server Board S5500WB TPS other channels hold the secondary image of the system memory. The integrated memory controller in the Intel® 5500 series alternates between both channels for read transactions. Under normal circumstances, write transactions are issued to both channels. Mirroring is only supported between Channels A & B and Channels D & E. The presence of a DIMM on Channel C or F causes the BIOS to disable Mirroring and revert to the Independent Channel mode.
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Intel® Server Board S5500WB TPS • 3.5.1 Functional Architecture Manageability Engine (ME) subsystem IOH24D PCI Express* PCI Express* Gen1 and Gen2 are dual-simplex, point-to point serial differential low-voltage interconnects. The signaling bit rate is 2.5 Gb/s one direction per lane for Gen1 and 5.0 Gb/s one direction per lane for Gen2. Each port consists of a transmitter and receiver pair. A link between the ports of two devices is a collection of lanes (x1, x2, x4, x8, x16, and so forth).
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Functional Architecture Intel® Server Board S5500WB TPS The Intel® 5500 Chipset IOH supports DMA remapping from inbound PCI Express* memory Guest Physical Address (GPA) to Host Physical Address (HPA). PCI Express* devices are directly assigned to a virtual machine leading to a robust and efficient virtualization. 3.6 Management Engine The Management Engine (ME) is an embedded ARC controller within the IOH.
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Intel® Server Board S5500WB TPS Functional Architecture • System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices • Low Pin Count (LPC) interface support • Serial Peripheral Interface (SPI) support 3.7.1 Serial ATA Support The ICH10R has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and data transfer rates of up to 3.0 Gb/s. The six SATA ports on the server board are numbered SATA-1 through SATA-6.
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Functional Architecture 3.8 Intel® Server Board S5500WB TPS • Two internal 2x5 headers are provided, capable of supporting two optional USB 2.0 ports each, typically, one header supports Front panel USB and one supports an internal third party management card.
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Intel® Server Board S5500WB TPS Functional Architecture • • • NIC 2 MAC address – Assigned the NIC 1 MAC address +1 Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2 Intel® Remote Management Module 3 (Intel® RMM3) MAC address – Assigned the NIC 1 MAC address +3 ® The Intel Server Board S5500WB has a white MAC address sticker included with the board. The sticker displays the NIC 1 MAC address in both bar code and alphanumeric formats. 3.8.
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Functional Architecture Intel® Server Board S5500WB TPS • LPC to SPI Bridge for system BIOS support • SMI and PME support • ACPI compliant • Wake-up control The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features: 32 • USB 2.
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Intel® Server Board S5500WB TPS Functional Architecture Figure 19. Integrated BMC Hardware 3.9.1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These interfaces are not shared with the host system. At any time, you can enable only one dedicated interface for management traffic. The default active interface is the NIC 1 port. For these channels, you can enable support for IPMI-over-LAN and DHCP.
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Functional Architecture Intel® Server Board S5500WB TPS 3.11 Wake-up Control Wake from S1 is supported on LAN, USB, Serial port, and PCI Express* slots. 3.12 Integrated Video Support The SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution in 8 / 16 / 32 bpp modes under 2D. It also supports both CRT and LCD monitors up to a 200 Hz vertical refresh rate. The video is accessed using a standard 15-pin VGA connector found in the I/O panel area of the server board.
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Intel® Server Board S5500WB TPS Functional Architecture Table 10. Dual Video Options Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled 3.12.3 Shaded if onboard video is set to "Disabled" Front Panel Video ® The Intel Server Board S5500WB provides a mechanism to support video to the front panel via the use of an internal header. When a monitor is plugged into the front panel video connector, the rear panel video stream is disconnected.
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Functional Architecture Intel® Server Board S5500WB TPS The PEWIDTH is pulled up to 3.3 V Aux on the baseboard and grounded, if necessary, by the riser. The baseboard provides an inverter and voltage level translator before passing this signal to the IOH. 3.13.3 Slot 1 PCI Express* x8 Connector Slot 1 provides a PCI Express* x4 bus on an x8 connector, if provided, for use in a 2U chassis that uses LP boards without risers.
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Intel® Server Board S5500WB TPS Intel® I/O Expansion Modules Intel® I/O Expansion Modules 4. The Intel® Server Board S5500WB supports a variety of I/O Module options using 2x4 PCI Express* Gen2 Intel® I/O Expansion Module connectors on the rear of the server board. Each Intel® I/O Expansion Module connector is a 50-pin, surface mount, 0.8mm pitch, header.
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Intel® I/O Expansion Modules Product Code Intel® Server Board S5500WB TPS Description AXX4GBIOMOD2 Quad port Gigabit Ethernet I/O Expansion Module based on the Intel® 82576EB Gigabit Ethernet Controller. AXXIBQDRMOD InfiniBand* I/O Expansion Module Single Port QDR. For more information, refer to the I/O modules in the Intel® I/O Expansion Modules Hardware Specification. 38 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS 5. Platform Management Features Platform Management Features This section explains BIOS and firmware (FW) requirements that drive specific hardware implementations of the platform. To a large extent, this is background information. 5.1 BIOS Feature Overview The Intel® Server Board S5500WB product uses the AMI Aptio v3.x code base. 5.1.1 EFI Support The platform BIOS is compiled to support the 64-bit EFI environment, natively.
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Platform Management Features Intel® Server Board S5500WB TPS The server management subsystem is available when the system is connected to wall power but not fully operational (S5 state); when the system is in a S1 sleep state or when the system is fully operational (S0 state). 5.2.1 Server Engines Pilot II Controller The center of the server management subsystem is the Server Engines Pilot II integrated Baseboard Management Controller.
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Intel® Server Board S5500WB TPS 5.2.3 Platform Management Features BMC Basic Features IPMI 2.0 Feature Description Compliance to IPMI 2.
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Platform Management Features 5.3 Intel® Server Board S5500WB TPS Management Engine (ME) 5.3.1 Overview ® The Intel Server Platform Services (SPS) is a set of manageability services provided by the firmware executing on an embedded ARC controller within the IOH. This management controller is also commonly referred to as the Management Engine (ME).
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Intel® Server Board S5500WB TPS • 5.5.2 Platform Management Features Wake IPMI command is supported (BMC function no additional hardware requirement) for all supported Sleep states. PCI Express* Power management L0 and L3 power management states are supported on all PCI Express* slots and embedded end points. 5.5.3 PMBus* Power supplies that have PMBus* 1.1 are supported and required to support Intel® Dynamic Power Node Manager.
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Platform Management Features Main Bus Power Rail Sub Bus Intel® Server Board S5500WB TPS Power Rail Device DB803 0xDC CPU0 DIMM 1A CPU0 DIMM 2A CPU0 DIMM 1B CPU0 DIMM 1C CPU0 DIMM 1D CPU0 DIMM 2D 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC CPU0 DIMM 1E CPU0 DIMM 1F Sensor IPMI 3V3SB 3V3SB NA NA NA IPMI IPMI NA 5VSB 5V LAN 3V3SB NA NA Link 3V3SB NA NA Spare DDC 44 3V3SB 3V3SB PWR 5V NA DDC NA 5V SMBus Address 0xAE IBMC SMBus 1 Temp Sensor FP Temp Sensor FP FRU Baseboard FRU CPU IOH
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Intel® Server Board S5500WB TPS 6. Configuration Jumpers Configuration Jumpers The following table provides a summary and description of configuration, test, and debug jumpers on the Intel® Server Board S5500WB. The server board has several 3-pin jumper blocks that can be used.
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Configuration Jumpers Intel® Server Board S5500WB TPS Table 16: Server Board Jumpers (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2) Jumper Name Jumper Position J1B5: BMC Force Update jumper 1-2 Mode of Operation Normal 2-3 Update IBMC GPIO[1] is pulled LOW. J1C2: Password Clear 1-2 Normal ICH10R INTRUDER# pin is pulled HIGH. Default position. 2-3 Clear Password ICH10R INTRUDER# pin is pulled LOW. 1-2 Normal ICH10R GPIO [55] is pulled HIGH. Default position.
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Intel® Server Board S5500WB TPS Configuration Jumpers 4. Close the server chassis. 5. Reconnect the AC cord and power up the server. 6. Perform the BMC firmware update procedure as documented in the README.TXT file included in the given BMC firmware update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating the BMC is still in update mode. 7. Power down and remove the AC power cord. 8. Open the server chassis. 9.
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Configuration Jumpers Intel® Server Board S5500WB TPS The password is now cleared and you can reset it by going into the BIOS setup. 6.1.3 BIOS Recovery Mode (J1C3) The Intel® Server Board S5500WB uses BIOS recovery to repair the system BIOS from flash corruption in the main BIOS and Boot Block. This 3-pin jumper is used to reload the BIOS when the image is suspected to be corrupted. For directions on how to recover the BIOS, refer to the specific BIOS release notes. Table 19.
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Intel® Server Board S5500WB TPS 6.1.4 Configuration Jumpers Reset BIOS Configuration (J1B4) This jumper used to be the CMOS Clear jumper. Since the previous generation, the BIOS has moved CMOS data to the NVRAM region of the BIOS flash. The BIOS checks during boot to determine if the data in the NVRAM needs to be set to default. Table 20. Reset BIOS Jumper Jumper Position Mode of Operation 1-2 Normal 2-3 Reset BIOS Configuration Note ICH10R RTCRST# pin is pulled HIGH. Default position.
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Configuration Jumpers Intel® Server Board S5500WB TPS J6A3, 2-3 jumpered: External video connector is primary, but video can come out of internal video connector if you connect to it. 6.1.6 ME Firmware Force Update (J7A2) Pins ME Firmware Update Mode 1-2 Disabled (Default) 2-3 Enabled The ME firmware consists of two operational images and a recovery image. During boot, the recovery loader is started first and it tries to load the active firmware image by running the loader of this image.
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Intel® Server Board S5500WB TPS Connector / Header Locations and Pin-out 7. Connector / Header Locations and Pin-out 7.1 Power Connectors Table 22. SSI SKU 24-pin 2x12 Connector (J9B1) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name Pin +3.3V +3.3V GND +5V GND +5V GND PWR_GD SB5V +12V +12V +3.3V 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name +3.3V -12V GND PS_ON GND GND GND NC +5V +5V +5V GND Table 23.
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Connector / Header Locations and Pin-out Intel® Server Board S5500WB TPS Pin 1 2 3 4 5 6 7 8 Signal Name GND GND GND GND +12V +12V +12V +12V Table 26. 12-V Only Power Control (replaces the 1x5 power control) (J9D1) (FOXCONN ELECTRONICS INC HF1107V-P1 or TYCO ELECTRONICS CORPORATION 5-104809-6) Pin Signal Name 1 2 3 SMB_PWR_CLK SMB_PWR_DAT SMB_PWR_ALRT 4 5 6 7 Remote Sense Return 12V Remote Sense PS_ON 5V S/B Table 27.
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Intel® Server Board S5500WB TPS 7.2 7.2.1 Connector / Header Locations and Pin-out System Management Headers Intel® Remote Management Module 3 (Intel® RMM3) Connector A 34-pin Intel® RMM 3 connector (J5B1) is included on the server board to support the optional Intel® Remote Management Module 3. There is no support for third-party management cards on this server board.
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Connector / Header Locations and Pin-out Intel® Server Board S5500WB TPS If this switch is used while the system power is still applied, then the main power rail regulators is disabled first, then the main 3.3V S/B regulator is disabled, removing power from the BMC. The usage of this header is to recover a non-responsive board, possibly caused by a hung BMC. 7.2.3 Hard Drive Activity (Input) LED Header Table 47. SATA HDD Activity (Input) LED Header (J1E3) Pin 1 2 7.2.
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Intel® Server Board S5500WB TPS Connector / Header Locations and Pin-out Pin 11 Signal Name FP_PWR_BTN_N Pin 12 Signal Name NIC1_ACT_LED_N 13 GND (Power Button GND) 14 NIC1_LINK_LED_N 15 BMC_RST_BTN_N 16 SMB_SENSOR_3V3STB_DATA 17 GND (Reset GND) 18 SMB_SENSOR_3V3STB_CLK 19 FP_ID_BTN_N 20 FP_CHASSIS_INTRU 21 NC 22 NIC2_ACT_LED_N 23 FP_NMI_BTN_N 24 NIC2_LINK_LED_N Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel
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Connector / Header Locations and Pin-out Intel® Server Board S5500WB TPS to generate an NMI (non-maskable interrupt). The NMI is captured by the BIOS during boot services time and by the operating system during runtime. During boot services time, the BIOS halts the system upon detection of the NMI. 7.3.4 Chassis Identify Button The front panel Chassis Identify button toggles the state of the chassis ID LED. If the LED is off, pushing the ID button lights the LED.
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Intel® Server Board S5500WB TPS Connector / Header Locations and Pin-out Table 34. System Status LED Color Green Green State Solid on ~1 Hz blink Amber ~1 Hz blink Revision 1.3 System Status Ok Degraded Non-Fatal Description System ready BIOS detected 1. Unable to use all of the installed memory (more than one DIMM installed).1 2. In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2). 1 3.
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Connector / Header Locations and Pin-out Color State System Status Amber Solid on Fatal Off Not ready N/A Intel® Server Board S5500WB TPS Description Fatal alarm – system has failed or shut down: BIOS Detected 1. DIMM failure when there is one DIMM present and no good memory is present.1 2. Run-time memory uncorrectable error in nonredundant mode.1 3. CPU configuration error (for instance, processor stepping mismatch). Integrated BMC Detected 1. CPU CATERR signal asserted. 2. CPU 1 is missing. 3.
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Intel® Server Board S5500WB TPS 7.4 Connector / Header Locations and Pin-out I/O Connectors 7.4.1 PCI Express* Connectors ® The Intel Server Board S5500WB has two PCI Express slots. The pin-outs for the slots are shown in the following tables. Table 36.
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Connector / Header Locations and Pin-out Pin Side B 34 PCI Express* Signal PETxN4 Intel® Server Board S5500WB TPS PCI Express* Signal GND Pin Side A 34 Pin Side B 76 PCI Express* Signal GND PCI Express* Signal PERxP14 Pin Side A 76 35 GND PERxP4 35 77 GND PERxN14 77 36 GND PERxN4 36 78 PETxP15 GND 78 37 PETxP5 GND 37 79 PETxN15 GND 79 38 PETxN5 GND 38 80 GND PERxP15 80 39 GND PERxP5 39 81 PRSNT2# PERxN15 81 40 GND PERxN5 40 82 RSVD GND 82 Table 37.
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Intel® Server Board S5500WB TPS Pin-Side B 39 40 41 42 43 44 45 46 47 48 49 7.4.2 Connector / Header Locations and Pin-out PCI Express* Spec Signal Description Pin-Side A GND GND 39 40 41 42 43 44 45 46 47 48 49 GND GND GND PRSNT2# GND 8X end PCI Express* Spec Signal Description GND GND GND GND GND VGA Connectors The following table details the pin-out definition of the external VGA connector (J6A1). Table 38.
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Connector / Header Locations and Pin-out 7.4.3 Intel® Server Board S5500WB TPS Pin Signal Name Pin Signal Name 7 9 11 Vsync Hsync KEY 8 12 GND GND VIDEO_IN_USE signal 13 DDC_SDA 14 GND 15 DDC_SCL 16 +5V NIC Connectors The server board provides two stacked RJ-45 / 2xUSB connectors side-by-side on the back edge of the board (J8A2, J9A1). The pin-out for NIC connectors are identical and are defined in the following table. Table 40.
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Intel® Server Board S5500WB TPS 7.4.4 Connector / Header Locations and Pin-out SATA Connectors The server board provides up to six SATA / SAS connectors: • SATA-0 (J9B2) • SATA-1 (J9B3) • SATA-2 (J9C1) • SATA-3 (J9C2) • SATA-4 (J9B5) • SATA-5 (J9B4) The pin configuration for each connector is identical and defined in the following table. Table 41. SATA Connectors Pin 1 2 3 4 5 6 7 7.4.
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Connector / Header Locations and Pin-out Intel® Server Board S5500WB TPS Table 42. 50-pin Intel® I/O Expansion Module Connector Pin-out (J2B1, J3B1) 64 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS 7.4.6 Connector / Header Locations and Pin-out Serial Port Connectors The server board provides one external RJ-45 Serial A port (J7A1) and one internal 9-pin serial B header (J1A2). The following tables define the pin-outs. Table 43. External RJ-45 Serial Port A (COM1) (J7A1) Pin 1 2 3 4 Signal Name Pin SPA_RTS SPA_DTR SPA_SOUT_N GND 5 6 7 8 Signal SPA_RI SPA_SIN SPA_DSR SPA_CTS Table 44. Internal 9-pin Serial B (COM2) (J1A2) Pin 1 3 5 7 9 7.4.
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Connector / Header Locations and Pin-out Intel® Server Board S5500WB TPS One low-profile 2x5 connectors (J1D4) on the server board provides an option to support lowprofile USB based embedded flash devices. The pin-out of the connector is detailed in the following table. Table 47. Low-Profile Internal USB Connector (J1E2) Pin 1 3 5 7 9 7.
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Intel® Server Board S5500WB TPS 8. Intel® Light-Guided Diagnostics Intel® Light-Guided Diagnostics The server boards have several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description the location and function of each LED on the server board. 8.1 5-V Standby LED Several server management features of this server board require a 5-V stand-by voltage is supplied from the power supply.
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Intel® Light-Guided Diagnostics 8.2 Intel® Server Board S5500WB TPS Fan Fault LEDs Fan fault LEDs are present for the six fans and are located near each CPU fan header. AF003115 E A B C F G H D Figure 23. Fan Fault LED Locations 8.3 A FLTMEM2R E FLTCPU1 B FLTMEM2 F FLTCPU1A C FLTCPU2A G FLTMEM1 D FLTCPU2 H FLTMEM1R System Status LED The server board provides LED for system status. The following figure shows the LED location. 68 Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS Intel® Light-Guided Diagnostics System Status LED AF003116 Figure 24. System Status LED Location The bi-color System Status LED operates as follows: Table 50. System Status LED Color Green State Solid on Revision 1.
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Intel® Light-Guided Diagnostics Color Green Amber 70 State ~1 Hz blink ~1 Hz blink Intel® Server Board S5500WB TPS System Status Degraded Non-Fatal Description System degraded: BIOS detected 1. Unable to use all of the installed memory (more than one DIMM installed).1 2. In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2). 1 3. PCI Express* correctable link errors. Integrated BMC detected 1.
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Intel® Server Board S5500WB TPS Color State System Status Amber Solid on Fatal Off Not ready N/A Intel® Light-Guided Diagnostics Description Fatal alarm – system has failed or shut down: BIOS Detected 1. DIMM failure when there is one DIMM present and no good memory is present.1 2. Run-time memory uncorrectable error in nonredundant mode.1 3. CPU configuration error (for instance, processor stepping mismatch). Integrated BMC Detected 1. CPU IERR signal asserted. 2. CPU 1 is missing. 3.
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Intel® Light-Guided Diagnostics 8.4 Intel® Server Board S5500WB TPS DIMM Fault LEDs Each DIMM slot has a DIMM Fault LED near the DIMM slot. A B C D E F G H AF003117 Figure 25. DIMM Fault LEDs Locations 72 A FLT_F E FLT_A2 B FLT_E F FLT_A1 C FLT_D1 G FLT_B D FLT_D2 H FLT_C Intel order number E53971-004 Revision 1.
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Intel® Server Board S5500WB TPS 8.5 Intel® Light-Guided Diagnostics POST Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server board in the rear I/O area of the server board by the VGA connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® Light-Guided Diagnostics 8.6 Intel® Server Board S5500WB TPS Front Panel Support The Intel® Server Board S5500WB supports SSI standard front panel boards. The front panel support is provided by a SSI compatible 2x12-pin signal connector. The front panel connector supports the following diagnostic LEDs. Table 51.
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Intel® Server Board S5500WB TPS Design and Environmental Specifications 9. Design and Environmental Specifications 9.1 Fan Speed Control Thermal Management Fan speed control supports the following thermal sensors: • Discrete board level digital thermal sensor TMP75 • Front panel Temp Sensor (if present) • CPU PECI DTS • DDR3 RDIMM TSOD Eight front system fan headers for four individual thermal zones • Zone 4 (mem2 fans) responds to memory2 and CPU2 temperatures.
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Design and Environmental Specifications Intel® Server Board S5500WB TPS The following tables show a basic location of the fan connectors on the board. The first line is the silk screen name of the connector; the second is the PWM signal name; the third is the Tach #; and the forth is the reference description. The last is the signal name associated with the fault LED signal. Figure 28: Location of Fan Connectors Table 52.
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Intel® Server Board S5500WB TPS Design and Environmental Specifications Table 53. Fan Connector Location & Detail CPU 2 Memory 2 FAN_CPU2 FAN_CPU2A FAN_MEM2 FAN_MEM2R PWM_CPU0 PWM_CPU0 PWM_MEM0 PWM_MEM0 Tach 3 Tach 7 Tach 4 Tach 4 & 8 J3E1 J2J2 J2J1 J1D5 LED_Fan_Fault_CPU0 LED_Fan_Fault_CPU0A LED_Fan_Fault_MEM0 LED_Fan_Fault_MEM0R Figure 29. Fans and Sensors Block Diagram 9.2 9.2.
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Design and Environmental Specifications • • • Intel® Server Board S5500WB TPS Tcontrol offset Temperature = -2° C Pos_hyst = 0° C Neg_hyst = 3° C Those parameters in turn set the following: • Upper = - CPU PECI Tcontrol + Tcontrol offset • Lower = - CPU PECI Tcontrol + Tcontrol offset – 3C 9.2.2 Memory Temperature Sensor DDR3 cooling requires thermal throttling to protect memory from overheating. The Intel® Server Board S5500WB supports both DDR3 UDIMM and DDR3 RDIMM.
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Intel® Server Board S5500WB TPS Design and Environmental Specifications A AF003062 Figure 30: Temp Sensor Location A 9.3 Location Description U4K3 Temp Sensor - TMP75 Heatsinks The Intel® Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling. Chipset and or voltage regulator heatsinks are compatible with the 1U usage. Revision 1.
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Design and Environmental Specifications Intel® Server Board S5500WB TPS Note: The Intel® Thermal Solution STS100P – Passive 1U/2U heatsink was tested for processors up to and including 95-W TDP (Thermal Design Power). Product order code: BXSTS100P 9.3.1 Unified Retention System Support The server board complies with the Intel® Unified Retention System (URS) and the Unified Backplate Assembly.
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Intel® Server Board S5500WB TPS 9.4 Design and Environmental Specifications Errors This section outlines how errors are routed in the hardware to ensure appropriate FW action (logging, fan control, system management, and so forth) is taken when an event occurs. 9.4.1 PROCHOT# PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the CPU.
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Power Subsystem Intel® Server Board S5500WB TPS 10. Power Subsystem 10.1 Server Board Power Distribution Figure 32. Power Distribution Diagram 10.2 Power Supply Compatibility The Intel® Server Board S5500WB is offered in two models: 82 • SSI SKU: This version of the server board is designed to work with an “off-the-shelf” multi-rail power supply that adheres to the SSI power specification: “Power Supply Design Guideline for 2008 Dual-Socket Servers and Workstations”.
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Intel® Server Board S5500WB TPS Power Subsystem The SSI uses the standard 24-pin and 8-pin power headers along with the 5pin Control connector. The 12-V only uses two 8-pin power headers, a 7-pin control header and a 6 pin HDD power connector. For maximum rack server efficiency, a DC 12-V only power supply is recommended. Appendix A shows connector pin outs. 10.3 Power Sequencing and Reset Distribution The IBMC device is integrated into the power control and reset logic of the system.
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Regulatory and Certification Information Intel® Server Board S5500WB TPS 11. Regulatory and Certification Information 11.1 Product Regulation Requirements Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations.
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Intel® Server Board S5500WB TPS Regulatory and Certification Information GOST – Listed on one System Certification (Russia) Belarus – Listed on one System Certification (Belarus) KCC Certification (Korea) Ecology Declaration (International) 11.
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Regulatory and Certification Information Intel® Server Board S5500WB TPS For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
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Intel® Server Board S5500WB TPS 11.3.3 Regulatory and Certification Information Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance. 11.3.4 BSMI (Taiwan) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 11.3.
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Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board.
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Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Table 55.
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Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS Table 56.
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Intel® Server Board S5500WB TPS QuickPath Interconnect (QPI) 0xA0h 0 0 1 1 0xA1h 0 0 1 1 0xA2h 0 0 1 1 0xA3h 0 0 1 1 0xA4h 0 0 1 1 0xA5h 0 0 1 1 Appendix A: POST Code LED Decoder 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 QPI Initialization QPI Initialization QPI Initialization QPI Initialization QPI Initialization QPI Initialization 0xA6h 1 0 1 0 0 1 1 0 QPI Initialization 0xA7h 0xA8h 0xA9h 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 0 1 QPI Initialization 0 QPI Initialization 1 Q
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Appendix A: POST Code LED Decoder USB 0x56h 0 1 0x57h 0 1 0x58h 1 0 0x59h 1 0 ATA/ATAPI/SATA 0x5Ah 0 1 0x5Bh 0 1 0x5Ch 1 0 0x5Dh 1 0 SMBUS 0x5Eh 1 0 0x5Fh 1 0 I/O Controller Hub 0x61h 0 1 Super I/O 0x63h 0 1 Local Console 0x70h 0 1 0x71h 0 1 0x72h 0 1 0x73h 0 1 Remote Console 0x78h 0 1 0x79h 0 1 0x7Ah 0 1 0x7Bh 0 1 Keyboard (only USB) 0x90h 0 1 0x91h 0 1 0x92h 0 1 0x93h 0 1 0x94h 0 1 0x96h 0 1 Mouse (only USB) 0x98h 0 1 0x99h 1 0 0x9Ah 0 1 0x9Bh 0 1 0x9Ch 0 1 Serial Port 0xA8h 0 1 0xA9h 0 1 0xAAh 0 1 0 1 0
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Intel® Server Board S5500WB TPS Fixed Media 0xB0h 1 0xB1h 1 Appendix A: POST Code LED Decoder Resetting fixed media device Disabling fixed media device Detecting presence of a fixed media device (SATA hard drive detection, and so forth) Enabling / configuring a fixed media device Reserved for fixed media 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0xB3h 0 1 0xB4h 0 1 Removable Media 0xB8h 0 1 0xB9h 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0xBCh 0 0 1
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Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS Pre-EFI Initialization Module (PEIM) / Recovery 0x30h 0 0 0 0 0 0 1 1 0x31h 0 0 0 0 0 1 1 1 0x34h 0 0 0 0 0 1 1 1 0x35h 0 0 0 0 1 1 1 1 0x36h 0 0 0 0 1 1 1 1 0x3Eh 0 0 0 1 1 1 1 1 0x3Fh 0 0 1 1 1 1 1 1 Crisis recovery initiated because of a user request Crisis recovery initiated by software (corrupt flash) Loading crisis recovery capsule Handing off control to the crisis recovery capsule Begin crisis recovery No crisis recovery cap
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Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Appendix B: Video POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Appendix B: Video POST Code Errors Intel® Server Board S5500WB TPS Error Code 5224 Password clear Jumper is Set. Error Message Major Response 8160 Processor 01 unable to apply microcode update Major 8161 Processor 02 unable to apply microcode update Major 8180 Processor 0x microcode update not found. Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure.
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Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Error Code 8566 Error Message DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error. Major Response 8567 DIMM_D2 Component encountered a Serial Presence Detection (SPD) fail error. Major 8568 DIMM_E1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8569 DIMM_E2 Component encountered a Serial Presence Detection (SPD) fail error.
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Appendix B: Video POST Code Errors Intel® Server Board S5500WB TPS Error Code 9687 Error Message DXE core component encountered a illegal software state error. Fatal Response 96A7 DXE boot services driver component encountered a illegal software state error. Fatal 96AB DXE boot services driver component encountered invalid configuration. Minor 96E7 SMM driver component encountered a illegal software state error. Fatal 0xA000 TPM device not detected.
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Intel® Server Board S5500WB TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Glossary Intel® Server Board S5500WB TPS Term HSC Hot-Swap Controller Definition HPA Host Physical Address Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel® Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management
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Intel® Server Board S5500WB TPS Glossary Term PSMI Power Supply Management Interface Definition PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) RMM3 Remote Management Module 3 SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM
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Reference Documents Intel® Server Board S5500WB TPS Reference Documents • • • • • • • • • • • • ACPI 3.0: http://www.acpi.info/spec.htm IPMI 2.0 Data Center Management Interface Specification v1.0, May 1, 2008.: www.intel.com/go/dcmi PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/ PCI Express* Base Specification Rev 2.0 Dec06: http://www.pcisig.com/ PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/ PMBus*: http://pmbus.org SATA 2.