Datasheet

Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
82 Datasheet
NOTE:
1. Synchronous assertion with active TDRY# ensures synchronization.
Table 43. Input Signals
Name Active Level Clock Si
g
nal Grou
p
Qualified
A20M# Low Asynch CMOS Input Always
1
BPRI# Low BCLK AGTL+ Input Always
BR1# Low BCLK AGTL+ Input Always
BCLK High — Clock Always
DEFER# Low BCLK AGTL+ Input Always
FLUSH# Low Asynch CMOS Input Always
1
IGNNE# Low Asynch CMOS Input Always
1
INIT# Low Asynch CMOS Input Always
1
INTR High Asynch CMOS Input APIC disabled mode
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMOS Input Always
PWRGOOD High Asynch CMOS Input Always
RESET# Low BCLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RSP# Low BCLK AGTL+ Input Always
SLP# Low Asynch CMOS Input During Stop-Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High — JTAG Input
TDI High TCK JTAG Input
TESTHI High Asynch Power/Other Always
TMS High TCK JTAG Input
TRST# Low Asynch JTAG Input
TRDY# Low BCLK AGTL+ Input