Datasheet

Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet 35
Figure 9. System Bus Reset and Configuration Timings
Figure 10. Power-On Reset and Configuration Timings
T
y
Safe Valid
T
z
Valid
T
v
T
w
T
x
T
u
T
t
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T
t
= T9 and T9' (GTL+ Input Hold Time)
T
u
= T8 and T8' (GTL+ Input Setup Time)
T
v
= T10 and T10' (RESET# Pulse Width)
T
w
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
PCD-764
BCLK
PWRGOOD
RESET#
T
a
T
b
V ,
CC
V
REF
D0007-02
V ,
CCP,
V
IL,max
Confi
g
uration
(
A20M#, IGNNE#,
INTR, NMI
)
T
c
Valid Ratio
V
IH,min
T
a
= T15 and T15'
(
PWRGOOD Inactive Pulse Width
)
T
b
= T10 and T10'
(
RESET# Pulse Width
)
T
c
= T20
(
Reset Confi
g
uration Si
g
nals
(
A20M#, IGNNE#, LINT[1:0]
)
Hold Time
)