Datasheet

Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
34 Datasheet
Figure 6. BCLK, PICCLK, and TCK Generic Clock Waveform
Figure 7. System Bus Valid Delay Timings
Figure 8. System Bus Setup and Hold Timings
000761a
1.7V (2.0V*)
1.25V
0.7V (0.5V*)
t
r
t
p
t
f
t
h
t
l
CLK
T
r
= T5, pT25, T34 (Rise Time)
T
f
= T6, T26, T35 (Fall Time)
T
h
= T3, T23, T32 (High Time)
T
l
= T4, T24, T33 (Low Time)
T
p
= T1, T22, T31 (BLCK, TCK, PCICLK Period)
Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK and TCK are referenced to
0.7 V and 1.7 V
CLK
Signal
000762b
T
x
T
x
T
pw
V Valid Valid
T
x
T7, T11, T29 (Valid Delay)
=
T
pw
T14, T15 (Pulse Wdith)=
V
1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=
CLK
Signal
000763b
VValid
T
s
T8, T12, T27 (Setup Time)=
T
h
T9, T13, T28 (Hold Time)=
V
1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=
T
h
T
s