Datasheet

Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet 31
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor core pins.
All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified to 2.5 V +5%. See Table 2 for recommended pull-up resistor values.
Table 18. System Bus AC Specifications (APIC Clock and APIC I/O)at the Processor Core Pins
1, 2, 3
T# Parameter Min Max Unit Fi
g
ure Notes
T21: PICCLK Frequency 2.0 33.3 MHz
T22: PICCLK Period 30.0 500.0 ns 6
T23: PICCLK High Time 12.0 ns 6
T24: PICCLK Low Time 12.0 ns 6
T25: PICCLK Rise Time 1.0 5.0 ns 6
T26: PICCLK Fall Time 1.0 5.0 ns 6
T27: PICD[1:0] Setup Time 8.0 ns 8 4
T28: PICD[1:0] Hold Time 2.5 ns 8 4
T29: PICD[1:0] Valid Delay 1.5 10.0 ns 7 4, 5, 6
Table 19. System Bus AC Specifications (TAP Connection)at the Processor Edge Fingers
1, 2, 3
T# Parameter Min Max Unit Fi
g
ure Notes
T30’: TCK Frequency 16.667 MHz
T31’: TCK Period 60.0 ns 6
T32’: TCK High Time 25.0 ns 6 @1.7 V
T33’: TCK Low Time 25.0 ns 6 @0.7 V
T34’: TCK Rise Time 5.0 ns 6 (0.7 V–1.7 V)
4
T35’: TCK Fall Time 5.0 ns 6 (1.7 V–0.7 V)
4
T36’: TRST# Pulse Width 40.0 ns 12 Asynchronous
T37’: TDI, TMS Setup Time 5.5 ns 11 5
T38’: TDI, TMS Hold Time 14.5 ns 11 5
T39’: TDO Valid Delay 2.0 13.5 ns 11 6, 7
T40’: TDO Float Delay 28.5 ns 11 6, 7
T41’: All Non-Test Outputs Valid Delay 2.0 27.5 ns 11 6, 8, 9
T42’: All Non-Test Inputs Setup Time 27.5 ns 11 6, 8, 9
T43’: All Non-Test Inputs Setup Time 5.5 ns 11 5, 8, 9
T44’: All Non-Test Inputs Hold Time 14.5 ns 11 5, 8, 9