Datasheet
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
30 Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. For a Reset, the clock ratio defined by these signals must be a safe value (their final or a lower multiplier) within this
delay unless PWRGOOD is being driven inactive.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor edge
fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified to 2.5 V +5%. See Table 2 for recommended pull-up resistor values.
Table 16. System Bus AC Specifications (Reset Conditions)
1
T# Parameter Min Max Unit Fi
g
ure Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
4 BCLKs 9
Before deassertion of
RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Hold Time
2 20 BCLKs 9
After clock that
deasserts RESET#
T18: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Setup Time
1ms9
Before deassertion of
RESET#
T19: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time
5 BCLKs 9
After assertion of
RESET#
2
T20: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Hold Time
220BCLKs9, 10
After clock that
deasserts RESET#
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers
1, 2, 3
T# Parameter Min Max Unit Fi
g
ure Notes
T21’: PICCLK Frequency 2.0 33.3 MHz
T22’: PICCLK Period 30.0 500.0 ns 6
T23’: PICCLK High Time 12.0 ns 6
T24’: PICCLK Low Time 12.0 ns 6
T25’: PICCLK Rise Time 1.0 5.0 ns 6
T26’: PICCLK Fall Time 1.0 5.0 ns 6
T27’: PICD[1:0] Setup Time 8.5 ns 8 4
T28’: PICD[1:0] Hold Time 3.0 ns 8 4
T29’: PICD[1:0] Valid Delay 3.0 12.0 ns 7 4, 5, 6