Datasheet
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
28 Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for AGTL+ signals are referenced to the BCLK rising edge at 0. 7 V at the processor edge fingers. All
AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor edge fingers.
4. Valid delay timings for these signals are specified into 50
Ω
to 1.5 V and with V
REF
at 1.0 V.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing.
8. Specification is for a maximum 1.0 V swing.
9. After V
CC
CORE
, V
CC
L2
, and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core pin. All
AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. Valid delay timings for these signals are specified into 25
Ω
to 1.5 V and with VREF at 1.0 V.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing.
8. Specification is for a maximum 1.0 V swing.
9. This should be measured after V
CC
CORE
, V
CCL2
, and BCLK become stable.
Table 12. System Bus AC Specifications (AGTL+ Signal Group)at the Processor Edge Fingers
1, 2, 3
T# Parameter Min Max Unit Fi
g
ure Notes
T7’: AGTL+ Output Valid Delay 0.71 4.66 ns 7 4
T8’: AGTL+ Input Setup Time 1.97 ns 8 5, 6, 7
T9’: AGTL+ Input Hold Time 1.61 ns 8 8
T10’: RESET# Pulse Width 1.00 ms 10 9
Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
1, 2, 3
T# Parameter Min Max Unit Fi
g
ure Notes
T7: AGTL+ Output Valid Delay -0.20 3.45 ns 7 4
T8: AGTL+ Input Setup Time 2.10 ns 8 5, 6, 7
T9: AGTL+ Input Hold Time 0.85 ns 8 8
T10: RESET# Pulse Width 1.00 ms 10 6, 9