Specifications

2-3
LOCAL X2APIC ARCHITECTURE
bit 10 to zero. Section 2.7, “x2APIC STATE TRANSITIONS” provides a detailed state
diagram for the state transitions allowed for the local APIC.
2.3 X2APIC MODE REGISTER INTERFACE
In xAPIC mode, the software model for accessing the APIC registers is through a
memory mapped interface. Specifically, the APIC registers are mapped to a 4K-Byte
region in the processor's memory address space, the physical address base of the
4K-Byte region is specified in the IA32_APIC_BASE MSR (Default value of
FEE0_0000H).
In x2APIC mode, a block of MSR address range is reserved for accessing APIC regis-
ters through the processor’s MSR address space. This section provides details of this
MSR based interface.
2.3.1 Instructions to Access APIC Registers
In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC regis-
ters. The MSR addresses for accessing the x2APIC registers are architecturally
defined and specified in Section 2.3.2, “APIC Register Address Space”. Executing the
RDMSR instruction with APIC register address specified in ECX returns the content of
bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are returned in
register EDX - these bits are reserved if the APIC register being read is a 32-bit
register. Similarly executing the WRMSR instruction with the APIC register address in
ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC register.
If the register is a 64-bit register then bits 0 to 31 of register EDX are written to bits
32 to 63 of the APIC register. The Interrupt Command Register is the only APIC
register that is implemented as a 64-bit MSR. The semantics of handling reserved
bits are defined in Section 2.3.3, “Reserved Bit Checking”.
2.3.2 APIC Register Address Space
The MSR address range between 0000_0800H through 0000_0BFFH is architectur-
ally reserved and dedicated for accessing APIC registers in x2APIC mode. Figure 2-2
provides the detailed list of the APIC registers in xAPIC mode and x2APIC mode. The
MSR address offset specified in the table is relative to the base MSR address of 800H.
The MMIO offset specified in the table is relative to the default base address of
FEE00000H.
There is a one-to-one mapping between the legacy xAPIC register MMIO offset and
the MSR address offset with the following exceptions:
• The Interrupt Command Register (ICR): The two 32-bit ICR registers in xAPIC
mode are merged into a single 64-bit MSR in x2APIC mode.
• The Destination Format Register (DFR) is not supported in x2APIC mode.