Specifications

2-2
LOCAL X2APIC ARCHITECTURE
2.2 DETECTING AND ENABLING X2APIC
A processor’s support to operate its local APIC in the x2APIC mode can be detected
by querying the extended feature flag information reported by CPUID. When CPUID
is executed with EAX = 1, the returned value in ECX[Bit 21] indicates processor’s
support for the x2APIC mode. If CPUID.(EAX=01H):ECX[Bit 21] is set, then the local
APIC in the processor supports the x2APIC capability and can be placed into the
x2APIC mode. This bit is set only when the x2APIC hardware is present.
• System software can place the local APIC in the x2APIC mode by setting the
x2APIC mode enable bit (bit 10) in the IA32_APIC_BASE MSR at MSR address
01BH. The layout for the IA32_APIC_BASE MSR is shown in Figure 2-1.
Table 2-1, “x2APIC operating mode configurations” describe the possible combina-
tions of the enable bit (EN - bit 11) and the extended mode bit (EXTD - bit 10) in the
IA32_APIC_BASE MSR.
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1),
switching back to xAPIC mode would require system software to disable the local
APIC unit. Specifically, attempting to write a value to the IA32_APIC_BASE MSR that
has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode will raise
a GP exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave
x2APIC mode using IA32_APIC_BASE would require a WRMSR to set both bit 11 and
Figure 2-1. IA32_APIC_BASE MSR Supporting x2APIC
Table 2-1. x2APIC Operating Mode Configurations
xAPIC global enable
(IA32_APIC_BASE[11])
x2APIC enable
(IA32_APIC_BASE[10]) Description
0 0 local APIC is disabled
01Invalid
1 0 local APIC is enabled in xAPIC mode
1 1 local APIC is enabled in x2APIC mode
BSP—Processor is BSP
EN—xAPIC global enable/disable
APIC Base—Base physical address
63 071011 8912
Reserved
36 35
APIC Base
Reserved
EXTD—Enable x2APIC mode