Specifications

2-20
LOCAL X2APIC ARCHITECTURE
A RESET in the disabled state places the x2APIC in the xAPIC mode. All APIC registers
(including the local APIC ID register) are initialized as described in Section 2.7.1.
An INIT in the disabled state keeps the x2APIC in the disabled state.
2.7.1.4 State Changes From xAPIC Mode to x2APIC Mode
After APIC register states have been initialized by software in xAPIC mode, a transi-
tion from xAPIC mode to x2APIC mode does not affect most of the APIC register
states, except the following:
• The Logical Destination Register is not preserved.
• Any APIC ID value written to the memory-mapped local APIC ID register is not
preserved.
• The high half of the Interrupt Command Register is not preserved.
2.8 CPUID EXTENSIONS AND TOPOLOGY ENUMERATION
For Intel 64 and IA-32 processors that support x2APIC, the CPUID instruction
provides additional mechanism for identifying processor topology information.
Specifically, a value of 1 reported by CPUID.01H:ECX[21] indicates that the
processor supports x2APIC and the extended topology enumeration leaf
(CPUID.0BH).
The extended topology enumeration leaf can be accessed by executing CPUID with
EAX = 0BH. Software can detect the availability of the extended topology enumera-
tion leaf (0BH) by performing two steps:
• Check maximum input value for basic CPUID information by executing CPUID
with EAX= 0. If CPUID.0H:EAX is greater than or equal or 11 (0BH), then proceed
to next step
• Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is avail-
able. The presence of CPUID leaf 0BH in a processor does not guarantee support for
x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and maximum input value for
basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not supported
on that processor.
The extended topology enumeration leaf is intended to assist software with enumer-
ating processor topology on systems that requires 32-bit x2APIC IDs to address indi-
vidual logical processors.
The basic concept of processor topology enumeration using 8-bit initial APIC ID
(CPUID.01H:EBX[31:24]) on legacy systems is similar to using 32-bit x2APIC ID
reported by CPUID leaf 0BH: apply appropriate bit masks on unique IDs to sort out
levels of topology in a system.
Legacy processor enumeration algorithm is based on examining the initial APIC IDs
and additional information from CPUID leaves 01H and 04H to infer system-wide