Specifications

2-18
LOCAL X2APIC ARCHITECTURE
• The local APIC ID is initialized by hardware with a 32 bit ID (x2APIC ID). The
lowest 8 bits of the x2APIC ID is the legacy local xAPIC ID, and is stored in the
upper 8 bits of the APIC register for access in xAPIC mode.
• The following APIC registers are reset to all zeros for those fields that are defined
in the xAPIC mode:
— IRR, ISR, TMR, ICR, LDR, TPR, Divide Configuration Register (See Chapter 8
of “Intel® 64 and IA-32 Architectures Software Developer’s Manual“, Vol. 3B
for details of individual APIC registers),
— Timer initial count and timer current count registers,
• The LVT registers are reset to 0s except for the mask bits; these are set to 1s.
• The local APIC version register is not affected.
• The Spurious Interrupt Vector Register is initialized to 000000FFH.
• The DFR (available only in xAPIC mode) is reset to all 1s.
• SELF IPI register is reset to zero.
Figure 2-9. Local x2APIC State Transitions with IA32_APIC_BASE, INIT, and RESET
xAPIC Mode
EN =1
Illegal
Transition
Init
EN=1, Extd=1
Extended
Invalid
State
Mode
Reset
Extd = 1
Illegal
Transition
EN = 0
EN = 0
Illegal
Transition
Extd = 0
Illegal
Transition
Extd = 0
EN=1, Extd=0
EN = 0
Extd = 1
Reset
Reset
Init
Init
Disabled
EN = 0
Extd = 0
Extd = 1
EN = 0