Specifications

2-16

LOCAL X2APIC ARCHITECTURE

Directed EOI capability is intended to enable system software to perform directed

EOIs to specific IOxAPICs in the system. System software desiring to perform a

directed EOI would do the following:

• inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt

Vector Register, and

• following the EOI to the local x2APIC unit for a level triggered interrupt, perform

a directed EOI to the IOxAPIC generating the interrupt by writing to its EOI

Supporting directed EOI capability would require system software to retain a

mapping associating level triggered interrupts with IOxAPICs in the system.

Bit 12 of the Spurious Interrupt Vector Register (SVR) in the local x2APIC unit

controls the generation of the EOI broadcast if the Directed EOI capability is

supported. This bit is reserved to 0 if the processor doesn't support Directed EOI. If

SVR[bit 12] is set, a broadcast EOI is not generated on an EOI cycle even if the asso-

ciated TMR bit is indicating the current interrupt is a level triggered interrupt. Layout

of the Spurious Interrupt Vector Register is shown in Figure 2-7.

The default value for SVR[bit 12] is clear, indicating that an EOI broadcast will be

performed.

The support for Directed EOI capability can be detected by means of bit 24 in the

Local APIC Version Register. This feature is supported in both the xAPIC mode and

Figure 2-7. Spurious Interrupt Vector Register (SVR) of x2APIC

Reserved

APIC Software Enable/Disable

8911

0: APIC Disabled

1: APIC Enabled

Spurious Vector

MMIO Address: FEE0 00F0H

MSR Address: 080FH

EOI Broadcast Disable