Specifications

2-13

LOCAL X2APIC ARCHITECTURE

2.4.3 Interrupt Command Register

In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure 2-

5. The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR in

xAPIC mode, except bit 12 (Delivery Status) is not used since it is not needed in

X2APIC mode.

The destination ID field is expanded to 32 bits in x2APIC mode.

A single MSR write to the Interrupt Command Register is required for dispatching an

interrupt in x2APIC mode. With the removal of the Delivery Status bit, system soft-

ware no longer has a reason to read the ICR. It remains readable only to aid in

Figure 2-5. Interrupt Command Register (ICR) in x2APIC Mode

1. WRMSR to the ICR MSR ignores bit 12 of its source operand. The value returned by RDMSR from

the ICR MSR into bit 12 of its destination is undefined.

31 0

Reserved

Vector

Destination Shorthand

810

Delivery Mode

000: Fixed

001: Reserved

00: No Shorthand

01: Self

111213141516171819

10: All Including Self

11: All Excluding Self

010: SMI

011: Reserved

100: NMI

101: INIT

110: Start Up

111: Reserved

Destination Mode

0: Physical

1: Logical

Level

0 = De-assert

1 = Assert

Trigger Mode

0: Edge

1: Level

Destination Field

Address: 830H (63 - 0)

Value after Reset: 0H

Reserved

Unused