Specifications

2-11

LOCAL X2APIC ARCHITECTURE

than 32 bits in its hardware. System software should be agnostic to the actual

number of bits that are implemented. All non-implemented bits will return zeros on

reads by software.

The APIC ID value of FFFF_FFFFH and the highest value corresponding to the imple-

mented bit-width of the local APIC ID register in the system are reserved and cannot

be assigned to any logical processor.

In x2APIC mode, the local APIC ID register is a read-only register to system software

and will be initialized by hardware. It is accessed via the RDMSR instruction reading

the MSR at address 0802H. Figure 2-3 provides the layout of the Local x2APIC ID

Each logical processor in the system (including clusters with a communication fabric)

must be configured with an unique x2APIC ID to avoid collisions of x2APIC IDs. On

DP and high-end MP processors targeted to specific market segments and depending

on the system configuration, it is possible that logical processors in different and "un-

connected" clusters power up initialized with overlapping x2APIC IDs. In these

configurations, a model-specific means may be provided in those product segments

to enable BIOS and/or platform firmware to re-configure the x2APIC IDs in some

clusters to provide for unique and non-overlapping system wide IDs before config-

uring the disconnected components into a single system.

2.4.2 Logical Destination Register

In x2APIC mode, the Logical Destination Register (LDR) is increased to 32 bits wide.

It is a read-only register to system software. This 32-bit value is referred to as

“logical x2APIC ID”. System software accesses this register via the RDMSR instruc-

tion reading the MSR at address 80DH. Figure 2-4 provides the layout of the Logical