Specifications

2-10
LOCAL X2APIC ARCHITECTURE
2.3.7 VM-exit Controls for MSRs and x2APIC Registers
The VMX architecture allows a VMM to specify lists of MSRs to be loaded or stored on
VMX transitions using the VMX-transition MSR areas (see VM-exit MSR-store address
field, VM-exit MSR-load address filed, and VM-entry MSR-load address field in Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B).
The X2APIC MSRs cannot to be loaded and stored on VMX transitions. A VMX transi-
tion fails if the VMM has specified that the transition should access any MSRs in the
address range from 0000_0800H to 0000_08FFH (the range used for accessing the
X2APIC registers). Specifically, processing of an 128-bit entry in any of the VMX-
transition MSR areas fails if bits 31:0 of that entry (represented as ENTRY_LOW_DW)
satisfies the expression: “ENTRY_LOW_DW & FFFFF800H = 00000800H”. Such a
failure causes an associated VM entry to fail (by reloading host state) and causes an
associated VM exit to lead to VMX abort.
2.4 EXTENDED PROCESSOR ADDRESSABILITY
This section provides details on extensions to the physical xAPIC ID and the logical
xAPIC ID to support extended processor addressability.
The x2APIC architecture also provides two destination modes - physical destination
mode and logical destination mode. Each logical processor in the system has a
unique physical xAPIC ID which is used for targeting interrupts to that processor in
physical destination mode. The local APIC ID register provides the physical destina-
tion mode 8-bit or 32-bit ID for the processor, depending on xAPIC mode or x2APIC
mode. Section 2.4.1 describes the 32-bit x2APIC ID in x2APIC mode.
Each logical processor in the system also can have a unique logical xAPIC ID which is
used for targeting interrupts to that processor in logical destination mode. The
Logical Destination Register specified in Section 2.4.2. It contains the logical x2APIC
ID for the processor in x2APIC mode.
2.4.1 Local APIC ID Register
In x2APIC mode, the local APIC ID register is increased to 32 bits wide. This enables
2^32 -1 processors to be addressable in physical destination mode. This 32-bit value
is referred to as “x2APIC ID”. A processor implementation may choose to support less
Table 2-3. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation
MMIO Interface MSR Interface
xAPIC mode Available GP Fault
x2APIC mode Behavior identical to xAPIC in globally
disabled state
Available