Specifications

2-9
LOCAL X2APIC ARCHITECTURE
last write to the ESR. Errors are collected regardless of LVT Error mask bit, but the
APIC will only issue an interrupt due to the error if the LVT Error mask bit is cleared.
In the x2APIC mode, the write of a zero value is enforced. Software writes zero’s to
the ESR to clear the error status. Writes of a non-zero value to the Error Status
Register in x2APIC mode will raise a GP fault.
The layout of ESR is shown in Figure 2-2. In x2APIC mode, a RDMSR or WRMSR to an
illegal register address raises a GP fault. In xAPIC mode, the equivalent MMIO
accesses would have generated an APIC error. So in the x2APIC mode, the Illegal
Register Address field in the Error Status register will not have any errors logged.
Write to the ICR (in xAPIC and x2APIC modes) or to SELF IPI register (x2APIC mode
only) with an illegal vector (vector <= 0FH) will set the "Send Illegal Vector" bit. On
receiving an IPI with an illegal vector (vector <= 0FH), the "Receive Illegal Vector"
bit will be set. On receiving an interrupt with illegal vector in the range 0H – 0FH, the
interrupt will not be delivered to the processor nor will an IRR bit be set in that range.
Only the ESR “Receive Illegal Vector” bit will be set.
If the ICR is programmed with lowest priority delivery mode then the "Re-directible
IPI" bit will be set in x2APIC modes (same as legacy xAPIC behavior) and the inter-
rupt will not be processed.
2.3.6 x2APIC Register Availability
The local APIC registers can be accessed via the MSR interface only when the local
x2APIC has been switched to the x2APIC mode as described in Section 2.2. Accessing
any APIC register in the MSR address range 0800H through 0BFFH via RDMSR or
WRMSR when the local APIC is not in x2APIC mode will cause the instructions to raise
a GP fault. In x2APIC mode, the memory mapped interface is not available and any
access to the MMIO interface will behave similar to that of a legacy xAPIC in globally
disabled state. Table 2-3 provides the interactions between the legacy & extended
modes and the legacy and register interfaces.
Figure 2-2. Error Status Register (ESR)
MSR Address: 828H
31
0
Reserved
78123456
Illegal Register Address
Received Illegal Vector
Send Illegal Vector
Redirectible IPI
Reserved