Specifications

Intel® Server Board S3420GPRX TPS Appendix C: POST Code Diagnostic LED Decoder
Revision 1.1
Intel order number E92065-001
125
Table 82. POST Progress Code LED Example
Upper Nibble LEDs Lower Nibble LEDs
MSB LSB
LED #7 LED #6 LED #5 LED #4 LED #3 LED #2 LED #1 LED #0
LEDs
8h 4h 2h 1h 8h 4h 2h 1h
Status
ON
OFF ON OFF ON OFF ON OFF
1 0 1 0 1 1 0 0
Results
Ah Ch
 Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are
concatenated as ACh.
Table 83. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble Lower Nibble
MSB LSB
Checkpoint
8h 4h 2h 1h 8h 4h 2h 1h
LED #7 #6 #5 #4 #3 #2 #1 #0
Description
Host Processor
0x04h X X X X X O X X
Early processor initialization (flat32.asm) where
system BSP is selected
0x10h
X X X O X X X X
Power-on initialization of the host processor (Boot
Strap Processor)
0x11h
X X X O X X X O
Host processor cache initialization (including AP)
0x12h
X X X O X X O X
Starting application processor initialization
0x13h
X X X O X X O O
SMM initialization
Chipset
0x21h X X O X X X X O
Initializing a chipset component
Memory
0x22h X X O X X X O X
Reading configuration data from memory (SPD on
FBDIMM)
0x23h X X O X X X O O Detecting presence of memory
0x24h X
X O X X O X X
Programming timing parameters in the memory
controller
0x25h X X O X X O X O
Configuring memory parameters in the memory
controller
0x26h X X O X X O O X
Optimizing memory controller settings
0x27h X X O X X O O O
Initializing memory, such as ECC init
0x28h X X O X O X X X
Testing memory
PCI Bus
0x50h X O X O X X X X Enumerating PCI buses
0x51h X O X O X X X O Allocating resources to PCI buses
0x52h X O X O X X O X Hot Plug PCI controller initialization
0x53h X O X O X X O O Reserved for PCI bus
0x54h X
O X O
X O X X Reserved for PCI bus
0x55h X
O X O
X O X O Reserved for PCI bus
0x56h X
O X O
X O O X Reserved for PCI bus
0x57h X
O X O
X O O O Reserved for PCI bus