® Intel Server Board SE7520JR2 Technical Product Specification Revision 1.
Revision History Intel® Server Board SE7520JR2 Revision History Date December 2003 Revision Number 0.5 Modifications June 2004 0.9 Memory Sub-system rewrite, BIOS Chapter Updated, Management Chapter re-write, Error Handling chapter re-write, several changes made to better reflect final design October 2004 1.0 First non-NDA release; Updated IRQ routing diagrams, Updated mBMC Sensor tables, Updates to Regulatory Information, Updated Sensor data tables Preliminary Release Revision 1.
Intel® Server Board SE7520JR2 Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Table of Contents Intel® Server Board SE7520JR2 Table of Contents 1. 2. 3. Introduction ........................................................................................................................ 19 1.1 Chapter Outline...................................................................................................... 19 1.2 Server Board Use Disclaimer ................................................................................ 20 Server Board Overview ............................
Intel® Server Board SE7520JR2 Table of Contents 3.2.2 PCI-X Hub (PXH) ................................................................................................... 33 3.2.2.1 Full-height Riser Slot.......................................................................................... 33 3.2.2.2 Low Profile Riser Slot......................................................................................... 33 3.2.2.3 I/OxAPIC Controller...............................................................
Table of Contents Intel® Server Board SE7520JR2 3.4.3 Interrupt Routing .................................................................................................... 52 3.4.3.1 Legacy Interrupt Routing.................................................................................... 52 3.4.3.2 APIC Interrupt Routing ....................................................................................... 53 3.4.3.3 Legacy Interrupt Sources ...........................................................
Intel® Server Board SE7520JR2 4.3 Table of Contents BIOS Power On Self Test (POST) ......................................................................... 81 4.3.1 User Interface ........................................................................................................ 81 4.3.1.1 System Activity Window ..................................................................................... 82 4.3.1.2 Splash Screen/Diagnostic Window ...........................................................
Table of Contents 5.1 Intel® Server Board SE7520JR2 Platform Management Architecture Overview ..................................................... 115 5.1.1 5V Standby .......................................................................................................... 116 5.1.2 IPMI Messaging, Commands, and Abstractions xxx............................................ 116 5.1.3 IPMI ‘Sensor Model’.............................................................................................
Intel® Server Board SE7520JR2 Table of Contents 5.3.17.2 User Model..................................................................................................... 134 5.3.17.3 Request/Response Protocol .......................................................................... 134 5.3.17.4 Host to mBMC Communication Interface ....................................................... 134 5.3.17.5 LAN Interface ..............................................................................................
Table of Contents 6.4.2 Diagnostic LEDs .................................................................................................. 167 6.4.3 POST Code Checkpoints..................................................................................... 168 6.4.4 Bootblock Initialization Code Checkpoints........................................................... 170 6.4.5 Bootblock Recovery Code Checkpoint ................................................................ 171 6.4.
Intel® Server Board SE7520JR2 8. Design and Environmental Specifications..................................................................... 202 8.1 Server Board SE7520JR2 Design Specification.................................................. 202 8.2 Power Supply Requirements ............................................................................... 202 8.2.1 Output Connectors............................................................................................... 202 8.2.2 Grounding ..
Table of Contents Intel® Server Board SE7520JR2 Appendix A: Integration and Usage Tips.............................................................................. 221 Glossary................................................................................................................................... 222 Reference Documents ............................................................................................................ 225 Revision 1.
Intel® Server Board SE7520JR2 List of Figures List of Figures Figure 1. SE7520JR2 Board Layout ........................................................................................... 23 Figure 2. Server Board Dimensions............................................................................................ 25 Figure 3. Server Board SE7520JR2 Block Diagram ................................................................... 26 Figure 4. CEK Processor Mounting ........................................
List of Tables Intel® Server Board SE7520JR2 List of Tables Table 1: Baseboard Layout Reference ....................................................................................... 24 Table 2: Processor Support Matrix ............................................................................................. 28 Table 3: Supported DDR-266 DIMM Populations ....................................................................... 39 Table 4: Supported DDR-333 DIMM Populations .............................
Intel® Server Board SE7520JR2 List of Tables Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections ........................................... 97 Table 34: BIOS Setup, Hard Disk Drive Sub-Menu Selections.................................................. 97 Table 35: BIOS Setup, Removable Drives Sub-menu Selections.............................................. 97 Table 36: BIOS Setup, CD/DVD Drives Sub-menu Selections ..................................................
List of Tables Intel® Server Board SE7520JR2 Table 68: Error Codes and Messages ...................................................................................... 162 Table 69: Error Codes Sent to the Management Module ......................................................... 164 Table 70: BIOS Generated Beep Codes................................................................................... 165 Table 71: Troubleshooting BIOS Beep Codes.............................................................
Intel® Server Board SE7520JR2 List of Tables Table 103: External USB Connector Pin-out ............................................................................ 197 Table 104: Internal 1x10 USB Connector Pin-out (J1F1) ......................................................... 198 Table 105: Internal 2x5 USB Connector (J1G1) ....................................................................... 198 Table 106: CPU1/CPU2 Fan Connector Pin-out (J5F2, J7F1) .................................................
List of Tables Intel® Server Board SE7520JR2 < This page intentionally left blank. > Revision 1.
Intel® Server Board SE7520JR2 1. Introduction Introduction This Technical Product Specification (TPS) provides detail to the architecture and feature set of the Intel® Server Board SE7520JR2. The target audience for this document is anyone wishing to obtain more in depth detail of the server board than what is generally made available in the board’s Users Guide. It is a technical document meant to assist people with understanding and learning more about the specific features of the board.
Introduction 1.2 Intel® Server Board SE7520JR2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components.
Intel® Server Board SE7520JR2 2. Server Board Overview Server Board Overview The Intel® Server Board SE7520JR2 is a monolithic printed circuit board with features that were designed to support the high density 1U and 2U server markets. 2.1 Server Board SE7520JR2 SKU Availability In this document, the name SE7520JR2 is used to describe the family of boards that are made available under a common product name.
Server Board Overview Intel® Server Board SE7520JR2 RJ45 Serial B Port o Two RJ45 NIC connectors o 15-pin video connector o Two USB 2.0 ports o U320 High density SCSI connector (Channel B) (SCSI SKU only) Internal IO Connectors / Headers o Two onboard USB port headers. Each header is capable of supporting two USB 2.0 ports.
Intel® Server Board SE7520JR2 Server Board Overview 3 1 4 2 7 6 5 8 9 10 11 13 12 14 15 17 16 18 19 20 22 21 24 29 23 25 30 32 27 26 28 31 34 33 35 36 37 38 40 39 Figure 1. SE7520JR2 Board Layout Revision 1.
Server Board Overview Intel® Server Board SE7520JR2 Table 1: Baseboard Layout Reference Ref # 1 Description (J1A1) 2-Pin Chassis Intrusion Header (J1A2) 2-Pin Hard Drive Act LED Header (J1A4) Rolling BIOS Jumper Ref # Description 22 CPU #2 Fan Header 2 10-Pin DH10 Serial A Header 23 CPU #1 Fan Header 3 Ext SCSI Channel B Connector 24 5-pin Power Sense Header 4 USB Port 2 25 PXH – Chipset Component 5 USB Port 1 26 CPU #2 Socket 6 Video Connector 27 CPU #1 Socket 7 NIC #2 28 ICH
Intel® Server Board SE7520JR2 Server Board Overview The following mechanical drawing shows the physical dimensions of the baseboard. Figure 2. Server Board Dimensions Revision 1.
Functional Architecture 3. Intel® Server Board SE7520JR2 Functional Architecture This chapter provides a high-level description of the functionality associated with the architectural blocks that make up the Intel Server Board SE7520JR2. Note: This document describes the features and functionality of the Server Board SE7520JR2 when using standard on-board platform instrumentation.
Intel® Server Board SE7520JR2 3.1 Functional Architecture Processor Sub-system The support circuitry for the processor sub-system consists of the following: • • • • • • • Dual 604-pin zero insertion force (ZIF) processor sockets Processor host bus AGTL+ support circuitry Reset configuration logic Processor module presence detection logic BSEL detection capabilities CPU signal level translation Common Enabling Kit (CEK) CPU retention support 3.1.
Functional Architecture 3.1.5 Intel® Server Board SE7520JR2 Common Enabling Kit (CEK) Design Support The baseboard has been designed to comply with Intel’s Common Enabling Kit (CEK) processor mounting and heat sink retention solution. The baseboard will ship with a CEK spring snapped onto the bottom side of the board beneath each processor socket. The CEK spring is removable, allowing for the use of non-Intel heat sink retention solutions.
Intel® Server Board SE7520JR2 3.1.6.1 Functional Architecture Processor Family Intel® Xeon™ FSB Frequency 800 MHz Frequency 3.2 GHz Support Yes Intel® Xeon™ 800 MHz 3.4 GHz Yes Intel® Xeon™ 800 MHz 3.6 GHz Yes Processor Mis-population Detection The processors must be populated in the correct order for the processor front-side bus to be correctly terminated. CPU socket 1 must be populated before CPU socket 2.
Functional Architecture Intel® Server Board SE7520JR2 High and Low Ratio is determined and programmed to all processors. If there is no value that works for all installed processors, all processors not capable of speeds supported by the BSP are disabled and an error is displayed. 3.1.6.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intelsupplied data block (i.e., microcode update).
Intel® Server Board SE7520JR2 Functional Architecture BSP and starts executing from the reset vector (F000:FFF0h). A processor that does not perform the role of BSP is referred to as an application processor (AP). The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the machine to boot the operating system.
Functional Architecture Intel® Server Board SE7520JR2 • Memory Controller Hub (MCH) • I/O Controller Hub (ICH5-R) • PCI-X Hub (PXH) The following sub-sections provide an overview of the primary functions and supported features of each chipset component as they are used on the Server Board SE7520JR2. Later sections in this chapter provide more detail on the implementation of the sub-systems. 3.2.
Intel® Server Board SE7520JR2 Functional Architecture GB/s. One x8 interface is used as the interconnect between the MCH and PXH, while the other is configured as two separate x4 interfaces to the full height riser slot. The E7520 MCH is a root class component as defined in the PCI Express Interface Specification, Rev 1.0a. The PCI Express interfaces of the MCH support connection to a variety of bridges and devices compliant with the same revision of the specification.
Functional Architecture 3.2.2.3 Intel® Server Board SE7520JR2 I/OxAPIC Controller The PXH contains two I/OxAPIC controllers, both of which reside on the primary bus. The intended use of these controllers is to have the interrupts from PCI bus A connected to the interrupt controller on device 0, function 1 and have the interrupts on PCI bus B connected to the interrupt controller on device 0, function 3. 3.2.2.
Intel® Server Board SE7520JR2 Functional Architecture IDE channels of the ICH5R. One channel is accessed through the 40-pin connector on the baseboard. The signals of the second channel are routed to the 100-pin backplane connector for use in either the Intel Server Chassis SR1400 or SR2400 when integrated with a backplane for slim-line optical drive use. 3.2.3.3 SATA Controller The SATA controller supports two SATA devices, providing an interface for SATA hard disks and ATAPI devices.
Functional Architecture 3.2.3.6 Intel® Server Board SE7520JR2 Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA-compatible PIC described in the previous section, the ICH5-R incorporates the Advanced Programmable Interrupt Controller (APIC). 3.2.3.7 Universal Serial Bus (USB) Controller The ICH5-R contains an Enhanced Host Controller Interface (EHCI) for Universal Serial Bus, Revision 1.0-compliant host controller that supports USB high-speed signaling.
Intel® Server Board SE7520JR2 Functional Architecture The ICH5-R supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface: Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. See the System Management Bus (SMBus) Specification, Version 2.0 for more information. 3.
Functional Architecture Intel® Server Board SE7520JR2 X8, double row 256MB 512MB 1GB 2GB X4, single row 256MB 512MB 1GB 2GB X4, Stacked, double row 512MB 1GB 2GB 4GB DIMMs on channel ‘A’ are paired with DIMMs on channel ‘B’ to configure 2-way interleaving. Each DIMM pair is referred to as a bank. The bank can be further divided into two rows, based on single-sided or double-sided DIMMs. If both DIMMs in a bank are single-sided, only one row is said to be present.
Intel® Server Board SE7520JR2 Functional Architecture Using the following algorithm, BIOS configures the memory controller of the MCH to run in either dual channel mode or single channel mode: (1) If 1 or more fully populated DIMM banks are detected, the memory controller is set to dual channel mode. Otherwise, go to step (2) (2) If DIMM 1A is present, set memory controller to single channel mode A.
Functional Architecture Intel® Server Board SE7520JR2 E D/R D/R E E D/R D/R S/R S/R E D/R S/R Table 5: Supported DDR2-400 DIMM Populations Bank 3 – DIMMs 3A, 3B S/R Bank 2 – DIMMs 2A, 2B S/R Bank 1 – DIMMs 1A, 1B S/R E S/R S/R E E S/R E D/R D/R E E D/R MCH E S/R D/R S/R S/R D/R Note: On the Server Board SE7520JR2, when using all dual rank DDR-333 or DDR2-400 DIMMs, a total of four DIMMs can be populated.
Intel® Server Board SE7520JR2 Functional Architecture status of the extended memory test is displayed on the console. The status of base and extended memory tests are also displayed on an LCD control panel if present. The extended memory test is configured using the BIOS Setup Utility.
Functional Architecture Intel® Server Board SE7520JR2 Uncorrectable memory errors are critical errors that may cause the system to fail. The BIOS normally detects and logs these errors as IPMI SEL events for all management levels, except in the case described below. It is possible that a critical hardware error (uncorrectable memory or bus error) may prevent the BIOS from running, reporting the error, and restarting the system.
Intel® Server Board SE7520JR2 Functional Architecture engine logs the failure. Both types of errors may be reported via multiple alternate mechanisms under configuration control. The scrub hardware will also execute “demand scrub” writes when correctable errors are encountered during normal operation (on demand reads, rather than scrub-initiated reads). This functionality provides incremental protection against time-based deterioration of soft memory errors from correctable to uncorrectable.
Functional Architecture 3.3.6.5 Intel® Server Board SE7520JR2 DIMM Sparing Function To provide a more fault tolerant system, the Intel E7520 MCH includes specialized hardware to support fail-over to a spare DIMM device in the event that a primary DIMM in use exceeds a specified threshold of runtime errors. One of the DIMMs installed per channel, greater than or equal in size than all installed, will not be used but kept in reserve.
Intel® Server Board SE7520JR2 3.3.6.6 Functional Architecture Memory Mirroring The memory mirroring feature is fundamentally a way for hardware to maintain two copies of all data in the memory subsystem, such that a hardware failure or uncorrectable error is no longer fatal to the system.
Functional Architecture Intel® Server Board SE7520JR2 D I M M D I M M D I M M D I M M D I M M D I M M 3 A 3 B 2 A 2 B 1 A 1 B MC Mirror Primar Primar /Mirror Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only) These symmetry requirements are a side effect of the hardware mechanism for maintaining two copies of all main memory data while ensuring that each channel has a full copy of all data in preparation for fail-down to single-channel operation.
Intel® Server Board SE7520JR2 Functional Architecture the primary and mirror DIMMs, thereby distributing the thermal image of the workload across all populated DIMM slots, and reducing the chances of thermal-based memory traffic throttling.
Functional Architecture Intel® Server Board SE7520JR2 Table 7: PCI Bus Segment Characteristics PCI Bus Segment P32-A Voltage 5V Width 32-bits Speed 33 MHz Type PCI PCI I/O Card Slots None. Internal component use only P64-A 3.3 V 64-bits 100 MHz PCI-X Common riser slot capable of supporting fulllength PCI-X or PCI-E add-in cards P64-B 3.
Intel® Server Board SE7520JR2 Functional Architecture supports a maximum of 66MHz, the entire bus will throttle down to 66MHz to match the supported frequency of that card. When populating add-in cards, the add-in cards must be installed starting with the slot furthest from the baseboard. Ie) When using a three slot riser, a single PCI-X add-in card must be installed in the top PCI slot. A second add-in card must be installed in the middle slot, and so on.
Functional Architecture Intel® Server Board SE7520JR2 hierarchical PCI bus under the current bridge. The PCI bus number and the subordinate PCI bus number are the same in the last hierarchical bridge. 3.4.1.7 Device Number and IDSEL Mapping Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus address/data signals AD[31::11] for the PCI bus. Each IDSEL-mapped AD bit acts as a chip select for each device on PCI.
Intel® Server Board SE7520JR2 Functional Architecture Table 8: PCI Configuration IDs and Device Numbers PCI Device MCH host-HI bridge/DRAM controller IDSEL Bus# / Device# / Function# 00 / 00 / 0 MCH DRAM Controller Error Reporting 00/00/1 MCH DMA controller 00/01/00 MCH EXP Bridge A0 00/02/00 MCH EXP Bridge A1 00/03/00 MCH EXP Bridge B0 00/04/00 MCH EXP Bridge B1 00/05/00 MCH EXP Bridge C0 00/06/00 MCH EXP Bridge C1 00/07/00 MCH Extended Configuration 00/08/00 ICH5R Hub interface to P
Functional Architecture 3.4.1.8 Intel® Server Board SE7520JR2 Resource Assignment The resource manager assigns the PIC-mode interrupt for the devices that will be accessed by the legacy code. The BIOS configures the PCI Base Address Registers (BAR) and the command register of each device. Software must not make assumptions about the scan order of devices or the order in which resources are allocated to them. The BIOS supports the INT 1Ah PCI BIOS interface calls. 3.4.1.
Intel® Server Board SE7520JR2 Functional Architecture Both PCI and IRQ types of interrupts are handled by the ICH5-R. The ICH5-R translates these to the APIC bus. The numbers in the table below indicate the ICH5-R PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD) is connected. The ICH5-R I/O APIC exists on the I/O APIC bus with the processors.
Functional Architecture 3.4.3.3 Intel® Server Board SE7520JR2 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the Server Board SE7520JR2. The actual interrupt map is defined using configuration registers in the ICH5-R. Table 10: Interrupt Definitions ISA Interrupt IRQ0 Description Timer/counter, HPET #0 in legacy replacement Mode. In APIC mode, cascade from 8259 controller #1 IRQ1 Keyboard IRQ2 Slave controller INTR output.
Intel® Server Board SE7520JR2 3.4.3.5 Functional Architecture IRQ Scan for PCIIRQ The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels. The Server Board SE7520JR2 has an external PCI interrupt serializer for PCIIRQ scan mechanism of ICH5-R to support 16 PCIIRQs.
Functional Architecture Intel® Server Board SE7520JR2 Super I/O Timer Serialized IRQ Interface Keyboard Cascade Serial Serial ISA Floppy/IS SERIR SERIRQ ICH5-R Interrupt Routing ISA RTC SCI/ISA ISA ISA Mouse/IS Coprocessor P_IDE/IS Not Used USB 1.1 Controller #1 and #4 PIRQA Video PIRQB USB 1.1 Controller #3, Native IDE and SATA USB 1.1 Controller #2 PIRQ Option for SCI, TCO, HPET#0,1,2 PIRQE Option for SCI, TCO, HPET#0,1,2 PIRQF Option for SCI, TCO, HPET#0,1,2 PIRQ USB 2.
Intel® Server Board SE7520JR2 Functional Architecture Figure 10. PCI Interrupt Mapping Diagram Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card Revision 1.
Functional Architecture 3.4.4 Intel® Server Board SE7520JR2 SCSI Support The SCSI sub-system consists of the LSI 53C1030 Dual Channel Ultra320 SCSI controller, one internal 80-pin connector (SCSI Channel A), one external high 80-pin density SCSI connector (SCSI channel B), and on-board termination for both SCSI channels. 3.4.4.
Intel® Server Board SE7520JR2 • • • • • Functional Architecture Quick arbitrate and select (QAS) Skew compensation Inter-symbol interference (ISI) compensation Cyclic redundancy check (CRC) Domain validation technology The LSI53C1030 contains the following SCSI performance features: • Supports Ultra320 SCSI • Paced transfers using a free running clock • 320 MB/s data transfer rate on each SCSI channel • Mandatory packetized protocol • Quick arbitrate and select (QAS) • Skew compensation with bus trainin
Functional Architecture Intel® Server Board SE7520JR2 • • Reduces Interrupt Service Routine (ISR) overhead with interrupt coalescing • Supports 32-bit or 64-bit data bursts with variable burst lengths • Supports the PCI Cache Line Size register • Supports the PCI Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple commands • Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, and Memory Write Block commands • Supports up to 8 PCI-X outstanding split transaction
Intel® Server Board SE7520JR2 Functional Architecture The BIOS initializes and supports ATAPI devices such as LS-120/240, CDROM, CD-RW and DVD. The BIOS initializes and supports S-ATA devices just like P-ATA devices. It initializes the embedded the IDE controllers in the chipset and any S-ATA devices that are connected to these controllers. From a software standpoint, S-ATA controllers present the same register interface as the P-ATA controllers.
Functional Architecture 3.4.6.1 Intel® Server Board SE7520JR2 SATA RAID The Intel® RAID Technology solution, available with the 82801ER ICH5 R (ICH5R), offers data striping for higher performance (RAID Level 0), alleviating disk bottlenecks by taking advantage of the dual independent SATA controllers integrated in the ICH5R. There is no loss of PCI resources (request/grant pair) or add-in card slot.
Intel® Server Board SE7520JR2 Functional Architecture Table 11: Video Modes 2D Mode Refresh Rate (Hz) 2D Video Mode Support 16 bpp 24 bpp Supported Supported 32 bpp Supported 640x480 60, 72, 75, 90, 100 8 bpp Supported 800x600 60, 70, 75, 90, 100 Supported Supported Supported Supported 1024x768 60, 72, 75, 90, 100 Supported Supported Supported Supported 1280x1024 43, 60 Supported Supported Supported Supported 1280x1024 70, 72 Supported Supported Supported 1600x1200 60, 66 S
Functional Architecture 3.4.7.3 Intel® Server Board SE7520JR2 CKE O Clock Enable for Memory CS#[1..0] O Chip Select for Memory DQM[7..0] O Memory Data Byte Mask DSF O Memory Special Function Enable HCLK O Memory Clock [11..0] O Memory Address Bus MD[31..0] I/O Memory Data Bus RAS# O Row Address Select WE# O Write Enable Dual video The BIOS supports single and dual video modes. The dual video mode is enabled by default.
Intel® Server Board SE7520JR2 3.4.8.1 Functional Architecture NIC Connector and Status LEDs The 82546GB drives the two LEDs that are located on each network interface connector. The link/activity LED to the left of the connector indicates network connection when on, and transmit/receive activity when blinking. The speed LED to the right of the connector indicates 1000Mbps operations when amber, 100Mbps operations when green, and 10-Mbps when off. 3.4.9 USB 2.
Functional Architecture Intel® Server Board SE7520JR2 Pin 2 Name GPIOE11/XA10 IO/GPIO I/O,I(E)1 SE7520JR2 Use XBUS_A<10> 3 GPIOE12/XA9 I/O,I(E)1 XBUS_A<9> 4 GPIOE13/XA8 I/O,I(E)1 XBUS_A<8> 5 GPIOE14/XA7 I/O,I(E)1 XBUS_A<7> 6 GPIOE15/XA6 I/O,I(E)1 XBUS_A<6> 7 GPIOE16/XA5 I/O,I(E)1 XBUS_A<5> 8 GPIOE17/XA4 I/O,I(E)1 XBUS_A<4> 14 GPIO20/XRD_XEN_L I/O XBUS_XRD_L 15 GPIO21/XWR_XRW_L I/O XBUS_XWR_L 16 GPIO22/XA3 I/O XBUS_A<3> 17 GPIO23/XA2 I/O XBUS_A<2> 18 GPIO24/XA1
Intel® Server Board SE7520JR2 3.4.10.2 Functional Architecture Serial Ports The baseboard provides two serial ports: an external RJ45 Serial B port, and an internal DH10 Serial A header. The following sub-sections provide details on the use of the serial ports. 3.4.10.2.1 Serial Port A Serial A is an optional port, accessed through a 9-pin internal DH-10 header. A standard DH10 to DB9 cable is used to direct Serial A out the back of a given chassis.
Functional Architecture Intel® Server Board SE7520JR2 Serial B SIO Bus Exchange Serial A BMC 2 to 1 Mux Level Shifter Level shifter Header Rear RJ45 Figure 12. Serial Port Mux Logic 3.4.10.2.4 Rear RJ45 Serial B Port Configuration The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device. Using an RJ45 connector for a serial port gives direct support for serial port concentrators, which are widely used in the high-density server market.
Intel® Server Board SE7520JR2 Functional Architecture Note: The appropriate RJ45-to-DB9 adapter should match the configuration of the serial device used. One of two pin-out configurations is used, depending on whether the serial device requires a DSR or DCD signal. The final adapter configuration should also match the desired pin-out of the RJ45 connector, as it can also be configured to support either DSR or DCD. 3.4.10.3 Removable Media Drives The BIOS supports removable media devices, including 1.
Functional Architecture 3.5 Intel® Server Board SE7520JR2 Configuration and Initialization This section describes the initial programming environment including address maps for memory and I/O, techniques and considerations for programming ASIC registers, and hardware options configuration. 3.5.1 Memory Space At the highest level, the Intel Xeon processor address space is divided into four regions, as shown in the following figure.
Intel® Server Board SE7520JR2 3.5.1.1 Functional Architecture DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs, and must be maintained for compatibility reasons. The region is divided into sub-regions as shown in the following figure.
Functional Architecture 3.5.1.1.1 Intel® Server Board SE7520JR2 DOS Area The DOS region is 512 KB in the address range 0 to 07FFFFh. This region is fixed and all accesses go to main memory. 3.5.1.1.2 ISA Window Memory The ISA Window Memory is 128 KB between the address of 080000h to 09FFFFh. This area can be mapped to the PCI bus or main memory. 3.5.1.1.3 Video or SMM Memory The 128 KB Graphics Adapter Memory region at 0A0000h to 0BFFFFh is normally mapped to the VGA controller on the PCI bus.
Intel® Server Board SE7520JR2 3.5.1.2 Functional Architecture Extended Memory Extended memory is defined as all address space greater than 1MB. Extended Memory region covers 8GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in the following figure. PCI memory space can be remapped to top of memory (TOM).
Functional Architecture 3.5.1.2.1 Intel® Server Board SE7520JR2 Main Memory All installed memory greater than 1MB is mapped to local main memory, up to 8GB of physical memory. Memory between 1MB to 15MB is considered to be standard ISA extended memory. 1MB of memory starting at 15MB can be optionally mapped to the PCI bus memory space. The remainder of this space, up to 8GB, is always mapped to main memory, unless TBSG SMM is used which is just under TOLM. The range can be from 128KB till 1MB.
Intel® Server Board SE7520JR2 3.5.1.4 Functional Architecture System Management Mode Handling The chipset supports System Management Mode (SMM) operation in one of three modes. System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions that can be configured using Intel Lindenhurst PF chipset.
Functional Architecture 3.5.2 Intel® Server Board SE7520JR2 I/O Map The baseboard I/O addresses are mapped to the processor bus or through designated bridges in a multi-bridge system. Other PCI devices, including the ICH5-R, have built-in features that support PC-compatible I/O devices and functions, which are mapped to specific addresses in I/O space. On SE7520JR2, the ICH5-R provides the bridge to ISA functions.
Intel® Server Board SE7520JR2 Functional Architecture Address (es) 0071h RTC Data Resource 0073h RTC Data Aliased from 0071h 0075h RTC Data Aliased from 0071h 0077h RTC Data Aliased from 0071h 0080h – 0081h BIOS Timer 0080h – 008F DMA Low Page Register 0090h – 0091h DMA Low Page Register (aliased) 0092h System Control Port A (PC-AT control Port) (this port not aliased in DMA range) 0093h – 009Fh DMA Low Page Register (aliased) 0094h Video Display Controller 00A0h – 00A1h Interrupt
Functional Architecture Intel® Server Board SE7520JR2 Address (es) 03F8h – 03FFh Serial Port A (primary) Resource 0400h – 043Fh DMA Controller 1, Extended Mode Registers 0461h Extended NMI / Reset Control 0480h – 048Fh DMA High Page Register 04C0h – 04CFh DMA Controller 2, High Base Register 04D0h – 04D1h Interrupt Controllers 1 and 2 Control Register 04D4h – 04D7h DMA Controller 2, Extended Mode Register 04D8h – 04DFh Reserved 04E0h – 04FFh DMA Channel Stop Registers 051Ch Software NM
Intel® Server Board SE7520JR2 3.5.3.1 Functional Architecture CONFIG_ADDRESS Register CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure. Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [7::1] select a specific register in the configuration space of the selected device or function on the bus. 3.
System BIOS 4. Intel® Server Board SE7520JR2 System BIOS The BIOS is implemented as firmware that resides in the Flash ROM. It provides hardwarespecific initialization algorithms and standard PC-compatible basic input/output (I/O) services, and standard Intel® Server Board features. The Flash ROM also contains firmware for certain embedded devices. These images are supplied by the device manufacturers and are not specified in this document.
Intel® Server Board SE7520JR2 System BIOS As such, the BIOS ID for this platform takes the following form: • SE7520JR2 supporting DDR memory SE7520JR22.86B.P.01.00.0002.081320031156 • SE7520JR2 supporting DDR2 memory SE7520JR23.86B.P.01.00.0002.081320031156 4.2 Flash Architecture and Flash Update Utility The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel.
System BIOS Intel® Server Board SE7520JR2 System Activity/State Splash Screen / Diagnostic Screen POST Activity Figure 18. POST Console Interface 4.3.1.1 System Activity Window The top row of the screen is reserved for the system state window. On a graphics console, the window is 640x48. On a text console, the window is 80x2.
Intel® Server Board SE7520JR2 System BIOS The Static Information Display area presents the following information: • • • • Copyright message BIOS ID Current processor configuration Installed physical memory size 4.3.1.2.2 Quiet Boot / OEM Splash Screen The BIOS implements Quiet Boot, providing minimal startup display during BIOS POST. System start-up must only draw the end user’s attention in the event of errors or when there is a need for user action.
System BIOS Intel® Server Board SE7520JR2 Table 17: Sample BIOS Popup Menu Please select boot device: 1st Floppy Hard Drives ATAPI CDROM LAN PXE EFI Boot Manager ↓and↑ to move selection Enter to select boot device ESC to boot using defaults 4.4 BIOS Setup Utility The BIOS Setup utility is provided to perform system configuration changes and to display current settings and environment information. The BIOS Setup utility stores configuration settings in system non-volatile storage.
Intel® Server Board SE7520JR2 System BIOS Key ↔ Option Select Menu Description The left and right arrow keys are used to move between the major menu pages. The keys have no affect if a sub-menu or pick list is displayed. Tab Select Field The Tab key is used to move between fields. For example, Tab can be used to move from hours to minutes in the time item in the main menu. - Change Value The minus key on the keypad is used to change the value of the current item to the previous value.
System BIOS Intel® Server Board SE7520JR2 Feature System Overview Options Help Text Description AMI BIOS Version N/A N/A BIOS ID string (excluding the build time and date) Build Date N/A N/A BIOS build date N/A N/A Processor brand ID string Speed N/A N/A Calculated processor speed Count N/A N/A Detected number of physical processors Size N/A N/A Amount of physical memory detected System Time HH:MM:SS Use [ENTER], [TAB] or [SHIFTTAB] to select a field.
Intel® Server Board SE7520JR2 4.4.2.2.1 System BIOS Processor Configuration Sub-menu Table 21: BIOS Setup, Processor Configuration Sub-menu Options Feature Options Configure Advanced Processor Settings Help Text Description Manufacturer Intel N/A Displays processor manufacturer string Brand String N/A N/A Displays processor brand ID string Frequency N/A N/A Displays the calculated processor speed FSB Speed N/A N/A Displays the processor frontside bus speed.
System BIOS 4.4.2.2.2 Intel® Server Board SE7520JR2 IDE Configuration Sub-menu Table 22: BIOS Setup IDE Configuration Menu Options Feature IDE Configuration Onboard P-ATA Channels Options Disabled Primary Secondary Both Help Text Description Disabled: disables the integrated P-ATA Controller. Primary: enables only the Primary P-ATA Controller. Secondary: enables only the Secondary P-ATA Controller. Both: enables both P-ATA Controllers. Controls state of integrated PATA controller.
Intel® Server Board SE7520JR2 Options System BIOS Feature Third IDE Master N/A Help Text Description While entering setup, BIOS auto Selects submenu with additional device details. detects the presence of IDE devices. This displays the status of auto detection of IDE devices. Fourth IDE Master N/A While entering setup, BIOS auto Selects submenu with additional device details. detects the presence of IDE devices. This displays the status of auto detection of IDE devices.
System BIOS Intel® Server Board SE7520JR2 Table 24: BIOS Setup, IDE Device Configuration Sub-menu Selections Feature Options Primary/Secondary/Third/Fourth IDE Master/Slave Device N/A Help Text Description N/A Display detected device info Vendor N/A N/A. Display IDE device vendor. Size N/A N/A Display IDE DISK size.
Intel® Server Board SE7520JR2 4.4.2.2.3 System BIOS Floppy Configuration Sub-menu Table 25: BIOS Setup, Floppy Configuration Sub-menu Selections Feature Floppy Configuration Options Floppy A Disabled 720 KB 3 1/2" Help Text Description Select the type of floppy drive connected to the system. 1.44 MB 3 1/2" 2.88 MB 3 1/2" Onboard Floppy Controller 4.4.2.2.4 Disabled Enabled Note: Intel no longer validates 720Kb & 2.88Mb drives. Allows BIOS to Enable or Disable Floppy Controller.
System BIOS 4.4.2.2.5 Intel® Server Board SE7520JR2 USB Configuration Sub-menu Table 27: BIOS Setup, USB Configuration Sub-menu Selections Feature USB Configuration Options Help Text Description USB Devices Enabled N/A N/A List of USB devices detected by BIOS. USB Function Disabled Enabled Enables USB HOST controllers. When set to disabled, other USB options are grayed out. Legacy USB Support Disabled Keyboard only Enables support for legacy USB.
Intel® Server Board SE7520JR2 Feature Device #n Options N/A Emulation Type Auto Floppy Forced FDD Hard Disk CDROM 4.4.2.2.6 System BIOS Help Text N/A Description Only displayed if a device is detected, includes a DeviceID string returned by the USB device. If Auto, USB devices less than 530MB will be emulated as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to boot as FDD (Ex. ZIP drive).
System BIOS Intel® Server Board SE7520JR2 Feature Options Slot 1 Option ROM Disabled Help Text Description PCI-X 64/133 Enabled Slot 2 Option ROM Disabled PCI-X 64/133 Enabled Slot 3 Option ROM Disabled PCI-X 64/133 Visible only when installed riser supports this slot. PCI-X 64/133 Visible only when installed riser supports this slot. PCI-X 64/133 Visible only when installed riser supports this slot. PCI-X 64/133 Visible only when installed riser supports this slot.
Intel® Server Board SE7520JR2 Feature DIMM 3A System BIOS Options Installed Not Installed Disabled Mirror Spare DIMM 3B Installed Not Installed Disabled Mirror Spare Extended Memory Test 1 MB 1 KB Every Location Help Text Description Informational display. Informational display. Settings for extended memory test Disabled Memory Retest Disabled Enabled If "Enabled", BIOS will activate and retest all DIMMs on the next system boot.
System BIOS 4.4.2.3.1 Intel® Server Board SE7520JR2 Boot Settings Configuration Sub-menu Selections Table 32: BIOS Setup, Boot Settings Configuration Sub-menu Selections Feature Boot Settings Configuration Quick Boot Options Disabled Enabled Quiet Boot Disabled Enabled (this is conflict with previous words in this doc. Based on my memory, it is enabled by default) Help Text Description Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.
Intel® Server Board SE7520JR2 4.4.2.3.2 System BIOS Boot Device Priority Sub-menu Selections Table 33: BIOS Setup, Boot Device Priority Sub-menu Selections Feature Options Boot Device Priority Help Text 1st Boot Device Varies Specifies the boot sequence from the available devices. A device enclosed in parenthesis has been disabled in the corresponding type menu. nth Boot Device Varies Specifies the boot sequence from the available devices.
System BIOS nth Drive Intel® Server Board SE7520JR2 Varies 4.4.2.4 Specifies the boot sequence from the available devices. Varies based on system configuration. Security Menu Table 37: BIOS Setup, Security Menu Options Feature Security Settings Administrator Password is Options N/A Help Text Description Install / Not installed Informational display. User Password is N/A Install / Not installed Informational display.
Intel® Server Board SE7520JR2 System BIOS Feature Secure Mode Boot Options Disabled Enabled Help Text When enabled, allows the host system to complete the boot process without a password. The keyboard will remain locked until a password is entered. A password is required to boot from diskette. Description This node is grayed out if a user password is not installed. Diskette Write Protect Disabled Enabled Disable diskette write protection when Secure mode is activated.
System BIOS Intel® Server Board SE7520JR2 Feature Late POST Timeout Options Disabled 5 minutes 10 minutes 15 minutes 20 minutes Help Text This controls the time limit for add-in card detection. The system is reset on timeout. Hard Disk OS Boot Timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes This controls the time limit allowed for booting an operating system from a Hard disk drive. The action taken on timeout is determined by the OS Watchdog Timer policy setting.
Intel® Server Board SE7520JR2 4.4.2.5.2 System BIOS Serial Console Features Sub-menu Selections Table 40: BIOS Setup, Serial Console Features Sub-menu Selections Feature Serial Console Features BIOS Redirection Port Options Disabled Serial A Serial B Help Text Description If enabled, BIOS uses the specified serial port to redirect the console to a remote ANSI terminal. Enabling this option disables Quiet Boot.
System BIOS Intel® Server Board SE7520JR2 Feature BIOS Event Logging Options Disabled Help Text Select enabled to allow logging of BIOS events. Description Enables BIOS to log events to the SEL. This option controls BIOS events only. Enabled If enabled, BIOS will detect and log events for system critical errors. Critical errors are fatal to system operation. These errors include PERR, SERR, ECC. Enable SMM handlers to detect and log events to SEL. Disabled Enables or Disables ECC Event Logging.
Intel® Server Board SE7520JR2 System BIOS The BIOS relies on specialized hardware and additional flash space to accomplish online update/rolling of the BIOS. To this end, the flash is divided into two partitions, primary and secondary. The active partition from which the system boots shall be referred to as the primary partition. The AMI FLASH update suite and Intel Online updates preserve the existing BIOS image on the primary partition. BIOS updates are diverted to the secondary partition.
System BIOS 4.5.1.4 Intel® Server Board SE7520JR2 BIOS Recovery The BIOS has a ROM image size of 2 MB. A standard 1.44MB floppy diskette cannot hold the entire ROM file due to the large file size. To compensate for this, a Multi-disk recovery method is available for BIOS recovery. The BIOS contains a primary and secondary partition, and can support rolling BIOS updates.
Intel® Server Board SE7520JR2 4.6 System BIOS OEM Binary System customers can supply 16 KB of code and data for use during POST and at run-time. Individual platforms may support a larger user binary. User binary code is executed at several defined hook points during POST. The user binary code is stored in the system flash. If no run-time code is added, the BIOS temporarily allocates a code. If run-time code is present, the BIOS shadows the entire block as though it were an option ROM.
System BIOS 4.7.1 Intel® Server Board SE7520JR2 Operating Model The following table summarizes the operation of security features supported by the BIOS. Some security features require the Intel Management Module (IMM) to be installed. These include “Diskette Write Protect”, “Video Blanking”, and “Power Switch inhibit.
Intel® Server Board SE7520JR2 System BIOS Administrator/User Passwords and F2 Setup Usage Model Notes: • • • Visible=option string is active and changeable Hidden=option string is inactive and not visible Shaded=option string is gray-out and view-only There are three possible password scenarios: Scenario #1 Administrator Password Is User Password Is Login Type: N/A Not Installed Not Installed Set Admin Password (visible) Set User Password (visible) User Access Level [Full]** (shaded) Clear User Passwo
System BIOS Intel® Server Board SE7520JR2 Set User Password (visible) User Access Level [Full] (visible) Clear User Password (hidden) Login Type: Set Admin Password (hidden) Set User Password (visible) User Access Level [Full] (Shaded) Clear User Password (hidden) 4.7.2 Password Clear Jumper If the user or administrator password(s) is lost or forgotten, moving the password clear jumper (board location J1H3) to the clear position will clear both passwords.
Intel® Server Board SE7520JR2 System BIOS PC200x specifications are intended for systems that are designed to work with Windows 2000* and Windows XP* class operating systems. The Hardware Design Guide (HDG) for the Windows XP platform is intended for systems that are designed to work with Windows XP class operating systems. Each specification classifies the systems further and has requirements based on the intended usage for that system.
System BIOS Intel® Server Board SE7520JR2 The BIOS supports a control panel sleep button. The sleep button may not be provided on all control panel designs. On systems where the sleep button is optional, a system configuration option will be provided to enable or disable the sleep button. The ACPI tables will be updated to indicate the presence or absence of the sleep button. Removal of the sleep button does not prevent an ACPI OS from entering a sleep state.
Intel® Server Board SE7520JR2 4.9.2.6 System BIOS Sleep to On (ACPI) If an operating system is loaded, the sleep button generates a wake event to the ACPI chipset and a request (via SCI) to the OS to place the system in the “On” state. The OS retains control of the system and OS policy determines what sleep state (if any) and sleep sources the system can wake from. 4.9.2.
System BIOS Intel® Server Board SE7520JR2 4.10 PXE BIOS Support The BIOS will support PXE-compliant implementations that: • • • Locate and configure all PXE-capable boot devices (UNDI Option ROMs) in the system, both built-in and add-ins. Supply a PXE according to the specification if the system includes a built-in network device. Meet the following specifications: System Management BIOS (SMBIOS) Reference Specification v2.2 or later.
Intel® Server Board SE7520JR2 Platform Management BIOS Console Redirection is intended to accomplish the implementation of VT-UTF8 console redirection support in Intel® server BIOS products.
Platform Management Intel® Server Board SE7520JR2 Element IPMI Channels, and Sessions On-Board Platform Instrumentation Limited Intel® Management Module Professional Edition Yes Intel® Management Module Advanced Edition Yes EMP (Emergency Management Port) - IPMI Messaging over Serial/Modem. This feature is also referred to as DPC (Direct Platform Control) over serial/modem.
Intel® Server Board SE7520JR2 5.1 Platform Management Platform Management Architecture Overview CPU1 LM 93 VID_CPU0[5:0] P1_VID[5:0] ProcHot VID_CPU1[5:0] P2_VID[5:0] ThermTrip Not Used P12V_CPU_SCALED P12V_SCALED P_VTT P1V5 Not Used P_VCCP0 P_VCCP1 P3V3 P5V P1V8_SCSI DDR Core DDR Vtt Gb LAN Core N12V_SCALED P3V3_STBY SCSIA_TERMPWR SCSIB_TERMPWR +12V1 +12V2 +12V3 FSB_Vtt Chipset_Core ICH_Core CPU1_Vccp CPU2_Vccp 3.3V +5V SCSI_Core Mem_Core Mem_Vtt GBIT _Core -12V +3.
Platform Management 5.1.1 Intel® Server Board SE7520JR2 5V Standby The power supply must provide a 5V Standby power source for the platform to provide any management functionality. 5V Standby is a low power 5V supply that is active whenever the system is plugged into AC power.
Intel® Server Board SE7520JR2 5.1.3 Platform Management IPMI ‘Sensor Model’ An IPMI-compatible ‘Sensor Model’ is used to unify the way that temperature, voltage, and other platform management status and control is represented and accessed. The implementation of this model is done according to command and data formats defined in the Intelligent Platform Management Interface Specification. The majority of monitored platform elements are accessed as logical ‘Sensors’ under this model.
Platform Management 5.1.4 Intel® Server Board SE7520JR2 Private Management Busses A ‘Private Management Bus’ is a single-master I2C bus that is controlled by the management controller. Access to any of the devices on the Private Management Bus is accomplished indirectly via commands to the management controller via the IPMB or system interfaces.
Intel® Server Board SE7520JR2 Platform Management These interfaces remain active on standby power, providing a mechanism where the SEL, SDR, and recovery control features can be accessed even when the system is powered down.
Platform Management Intel® Server Board SE7520JR2 • • Platform Event Filtering (PEF) • Keyboard Controller Style (KCS) IPMI-System Interface (Professional and Advanced systems only) • SMBus IPMI-System Interface (On-board Platform Instrumentation systems only) • Intelligent Chassis Management Bus (ICMB) support (Professional and Advanced systems only) • Remote Boot Control • Local and Remote Power On/Off/Reset Control • Local and Remote Diagnostic Interrupt (NMI) Control • Fault-Resilient Booting • Cont
Intel® Server Board SE7520JR2 5.2 Platform Management On-Board Platform Management Features and Functionality The National Semiconductor PC87431M mini-Baseboard Management Controller (mBMC) is an Application Specific Integrated Circuit (ASIC) with a Reduced Instruction Set Computer (RISC)based processor and many peripheral devices embedded into it. It is targeted for a wide range of remote-controlled platforms, such as servers, workstations, hubs, and printers.
Platform Management Intel® Server Board SE7520JR2 Server Management I2C Buses 5.2.1 The table below describes the server management I2C bus assignments and lists the devices that are connected to the indicated bus. The column labeled “I2C Bus ID” represents the physical I2C bus connected to the mBMC. Only the Peripheral SMBus is available for use with the Write-Read I2C IPMI command. Table 46: Server Management I2C Bus ID Assignments I2C Bus ID 5.2.
Intel® Server Board SE7520JR2 Platform Management Figure 21. External Interfaces to mBMC 5.3 mBMC Hardware Architecture The following figure shows an example of the internal functional modules of the mBMC in a block diagram. The mBMC controls various server management functions, such as the system power/reset control, a variety of types of sensor monitoring, system initialization, fault resilient booting (FRB).
Platform Management Intel® Server Board SE7520JR2 Figure 22. mBMC Block Diagram 5.3.1 Power Supply Interface Signals The mBMC supports two power supply control signals: Power On and Power Good. The Power On signal connects to the chassis power subsystem through the chipset and is used to request power state changes (asserted = request Power On). Power Good is a signal from the chassis power subsystem indicating current power state (asserted = power is on). Revision 1.
Intel® Server Board SE7520JR2 Platform Management The following figure shows the power supply control signals and their sources. To turn on the system, the mBMC asserts the Power On signal and waits for the Power Good signal to assert in response, indicating that DC power is on. Figure 23.
Platform Management 5.3.2 Intel® Server Board SE7520JR2 Power Control Sources The sources listed in the following table can initiate power-up and/or power-down activity.
Intel® Server Board SE7520JR2 5.3.5.2 Platform Management Reset Control Sources The following table shows the reset sources and the actions taken by the system. Table 48: System Reset Sources and Actions 5.3.5.
Platform Management • Intel® Server Board SE7520JR2 Combined power and reset button assertion If DC power is off, an assertion of the PWBTIN while the RSTIN is asserted generates an OEM-specific Control Panel event to PEF. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific offset - 07h. This PEF action initiates a BIOS CMOS clear request to the system BIOS.
Intel® Server Board SE7520JR2 5.3.5.4.2 Platform Management Fault / Status LED The following table shows mapping of sensors/faults to the LED state.
Platform Management 5.3.5.5.1 Intel® Server Board SE7520JR2 Chassis Intrusion Some platforms support chassis intrusion detection. On those platforms, the mBMC monitors chassis intrusion by polling the server input/output (SIO) device. The state of the chassis intrusion input is provided by the status register of the SIO device. A Chassis Intrusion event is logged in the System Event Log when a change in the input state is detected. 5.3.5.5.
Intel® Server Board SE7520JR2 Platform Management time, the LED will turn off. If the LED is on, a button press or IPMI Chassis Identify command turns off the LED. Upon assertion of the chassis identify button, a SEL event is generated by the chassis identity sensor button. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific offset - 1h. 5.3.
Platform Management 5.3.10.1 Intel® Server Board SE7520JR2 SEL Erasure It can take up to one minute to clear a System Event Log based upon other concurrent mBMC operations. 5.3.10.2 Timestamp Clock The mBMC maintains a four-byte internal timestamp clock used by the SEL and SDR subsystems. This clock is incremented once per second and is read and set using the Get SEL Time and Set SEL Time commands, respectively. The Get SDR Time command can also be used to read the timestamp clock.
Intel® Server Board SE7520JR2 5.3.12 Platform Management Field Replaceable Unit (FRU) Inventory Devices An enterprise-class system typically has FRU information for each major system board, (processor board, memory board, I/O board, etc.). The FRU data includes information such as serial number, part number, model, and asset tag. This information can be accessed in two ways: through IPMI FRU commands or by using Master Write-Read commands.
Platform Management 5.3.16 Intel® Server Board SE7520JR2 mBMC Self Test The mBMC performs various tests as part of its initialization. If a failure is determined (e.g., corrupt mBMC FRU, SDR, or SEL), the mBMC stores the error internally. 5.3.17 Messaging Interfaces This section describes the supported mBMC communication interfaces: • Host SMS Interface via SMBus interface • LAN interface using the LOM SMBus These specifications are defined in the following subsections. 5.3.17.
Intel® Server Board SE7520JR2 Platform Management • SMBus data signal (SDAH) • Optional SMBus alert signal (SMBAH). The signal notifies the host that the PC87431x has data to provide. When the system main power is off (PWRGD signal is low), the host interface signals are in TRI-STATE to perform “passive” bus isolation between the mBMC SCLH, SDAH and SMBAH signals and the SMBus controller signals.
Platform Management 5.3.18 Intel® Server Board SE7520JR2 LAN Channel Capability Privilege Levels Options User, Operator, Administrator Authentication Types None, Straight Password, MD5 Number of LAN Alert Destinations 1 Address Resolution Protocol (ARP) Gratuitous ARP Event Filtering and Alerting The mBMC implements most of the IPMI 1.5 alerting features. The following features are supported: • • PEF Alert over LAN 5.3.18.
Intel® Server Board SE7520JR2 Platform Management down, power cycle, and/or reset actions, the actions are performed according to PEF Action Priorities. Note: An action that has changed from delayed to non-delayed, or an action whose delay time has been reduced automatically has higher priority. The mBMC can be configured to log PEF actions as SEL events.
Platform Management Intel® Server Board SE7520JR2 mBMC sensors 01h – 08h are internal sensors to the mBMC and are used for event generation only. These sensors are not for use with the ‘Get Sensor Reading’ IPMI command and may return an error when read.
Platform Management Sensor # Intel® Server Board SE7520JR2 Sensor Type Event / Reading Type Event Offset Triggers Assert / Deassert PEF Action SDR Record Type 0Ah Physical Security 05h Sensor Specific 6Fh General Chassis Intrusion As & De General Chassis Intrusion Trig Offset X 02 CPU1 12v 0Bh Voltage 02h Threshold 01h [u,l][c,nc] As & De Analog R, T Fault LED Action 01 CPU2 12v 0Ch Voltage 02h Threshold 01h [u,l][c,nc] As & De Analog R, T Fault LED Action 01 BB +1.
Platform Management Intel® Server Board SE7520JR2 Event Offset Triggers Assert / Deassert PEF Action SDR Record Type Sensor # Event / Reading Type Sensor Type Tach Fan 6 20h Fan 04h Threshold 01h [u,l][ c,nc] As & De Analog R, T Fault LED Action 01 Tach Fan 7 21h Fan 04h Threshold 01h [u,l][ c,nc] As & De Analog R, T Fault LED Action 01 Tach Fan 8 22h Fan 04h Threshold 01h [u,l][ c,nc] As & De Analog R, T Fault LED Action 01 Tach Fan 9 23h Fan 04h Threshold 01h [u,
Intel® Server Board SE7520JR2 Platform Management Revision 1.
Platform Management 5.3.20 Intel® Server Board SE7520JR2 IMM BMC Sensor Support The following tables are for the built-in and the external sensors for the platform when either an Intel Management Module Professional or Advanced is installed. Power Unit Status Power Unit Redundancy Sensor Number 01h 02h Sensor Type Power Unit 09h Power Unit 09h Event Offset Triggers Assert / Deassert Readable Value / Offsets Standby Sensor Name Rearm Table 56.
Sensor Number Sensor Type Event / Reading Type Event Offset Triggers Assert / Deassert Readable Value / Offsets Standby Sensor Name Platform Management Rearm Intel® Server Board SE7520JR2 As & De – Trig Offset A – EventData Critical Inerrupt Sensor 07h Critical Interrupt 13h Sensor Specific 6Fh Front Panel NMI Bus Error Memory 08h Memory 0Ch Sensor Specific 6Fh Uncorrectable ECC As – Trig Offset A – As – Trig Offset A X As – As defined by IPMI A X Event Logging Disa
Standby Intel® Server Board SE7520JR2 Rearm Platform Management Tach Fan 1 40h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 2 41h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 3 42h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 4 43h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 5 44h Fan 04h Threshold 01h [u,l][nr,c,nc] As & De Analog R, T M – Tach Fan 6 45
Standby Platform Management Rearm Intel® Server Board SE7520JR2 Digital Fan 10 59h Fan 04h Digital Discrete 06h Performance Met or Lags As & De – Trig Offset M – Digital Fan 11 5Ah Fan 04h Digital Discrete 06h Performance Met or Lags As & De – Trig Offset M – LVDS SCSI channel 1 terminator fault 60h Terminator 1Ch Digital Discrete 06h Performance Met or Lags As – Trig Offset A – LVDS SCSI channel 2 terminator fault 61h Terminator 1Ch Digital Discrete 06h Performance Met
Sensor Number Sensor Type Standby Sensor Name Intel® Server Board SE7520JR2 Rearm Platform Management Sensor Specific 6Fh OEM System Boot Event (Hard Reset) PEF Action As – Trig Offset A – Event / Reading Type Event Offset Triggers Assert / Deassert Readable Value / Offsets EventData System Event 83h System Event 12h Button 84h Button 14h Sensor Specific 6Fh Power Button Sleep Button Reset Button As – Trig Offset A X SMI Timeout 85h SMI Timeout F3h Digital Discrete 03h St
Standby Sensor Name Platform Management Rearm Intel® Server Board SE7520JR2 Trig Offset M X Analog R, T A – Analog R, T A – As & De Analog R, T A – As & De Analog R, T A – – Trig Offset M – As & De – Trig Offset M – Transitioned to Non-Critical from OK As & De – Trig Offset M – Digital Discrete 07h Transitioned to Non-Critical from OK As & De – Trig Offset M – Voltage 02h Threshold 01h [u,l][ nr,c,nc] As & De Analog R, T A – Voltage 02h Threshold 01h
DIMM 4 DIMM 5 DIMM 6 5.
Intel® Server Board SE7520JR2 6. Error Reporting and Handling Error Reporting and Handling This section defines how errors are handled. Also discussed is the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In addition, error-logging techniques are described and beep codes and POST messages are defined.
Error Reporting and Handling Intel® Server Board SE7520JR2 system reset (ASR). The Sahalee BMC retains status bits that can be read by the BIOS later in the POST for the purpose of disabling the previously failing processor, logging the appropriate event into the System Event Log (SEL), and displaying an appropriate error message to the user. Options are provided by the BIOS to control the policy applied to FRB2 failures.
Intel® Server Board SE7520JR2 Error Reporting and Handling If the BIOS is going to boot to a known PXE-compliant device, then the BIOS reads a user option for OS Watchdog Timer for PXE Boots and either disables the timer or enables the timer with a value read from the option (5, 10, 15, or 20 minutes). If the OS Watchdog Timer is enabled, the timer is repurposed as an OS Watchdog Timer and is referred to by that title as well.
Error Reporting and Handling Intel® Server Board SE7520JR2 does not alter the BSP and attempts to boot from the original BSP. Error messages are displayed on the console, and errors are logged in the event log of a processor failure. If the user replaces a processor that has been marked bad by the system, the system must be informed about this change by running BIOS Setup and selecting that processor to be retested.
Intel® Server Board SE7520JR2 Error Reporting and Handling The following table shows memory error handling with both a mBMC and Sahalee BMC. Table 57: Memory Error Handling mBMC vs Sahalee Memory with RAS mode Sparing mode / Mirroring mode Server with mBMC Server with IMM Sahalee BMC When Sparing or Mirroring occurs: - BIOS will not report memory RAS configuration to mBMC. - BIOS will light the faulty DIMM LED. When Sparing or Mirroring occurs: - BIOS will report memory RAS configuration to BMC.
Error Reporting and Handling Intel® Server Board SE7520JR2 In non-RAS mode, BIOS will assert a Non-Maskable-Interrupt (NMI) on the first Double Bit ECC (DBE) error. Table 58: Memory Error Handling in non-RAS mode Non-RAS mode Single Bit ECC (SBE) errors Double Bit ECC (DBE) errors 6.2.3 Server with mBMC SBE error events will not be logged. Server with IMM Sahalee BMC SBE error events will be logged in SEL. On the 10th SBE error, BIOS will: - Disable SBE detection in chipset.
Intel® Server Board SE7520JR2 6.3 Error Reporting and Handling Error Logging This section defines how errors are handled by the system BIOS. Also discussed is the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In addition, error-logging techniques are described and beep codes for errors are defined.
Error Reporting and Handling 6.3.4 Intel® Server Board SE7520JR2 Memory Bus Error The hardware is programmed to generate an SMI on single-bit data errors in the memory array if ECC memory is installed. The SMI handler records the error and the DIMM location to the system event log. Double-bit errors in the memory array are mapped to the SMI because the mBMC cannot determine the location of the bad DIMM. The double-bit errors may have corrupted the contents of SMRAM.
Intel® Server Board SE7520JR2 Error Reporting and Handling Gate20 Error The BIOS is unable to properly control the motherboard’s Gate A20 function, which controls access of memory over 1 MB. This may indicate a problem with the motherboard. Multi-Bit ECC Error This message will only occur on systems using ECC enabled memory modules. ECC memory has the ability to correct single-bit errors that may occur from faulty memory modules.
Error Reporting and Handling Message Displayed Primary Slave Hard Disk Error Secondary Master Hard Disk Error Secondary Slave Hard Disk Error 3rd Master Hard Disk Error rd 3 Slave Hard Disk Error 4th Master Hard Disk Error 4th Slave Hard Disk Error 5th Master Hard Disk Error 5th Slave Hard Disk Error 6th Master Hard Disk Error 6th Slave Hard Disk Error Primary Master Drive - ATAPI Incompatible Primary Slave Drive - ATAPI Incompatible Intel® Server Board SE7520JR2 Description detect and confi
Intel® Server Board SE7520JR2 Message Displayed Secondary Master Drive - ATAPI Incompatible Secondary Slave Drive - ATAPI Incompatible 3rd Master Drive - ATAPI Incompatible 3rd Slave Drive - ATAPI Incompatible 4th Master Drive - ATAPI Incompatible 4th Slave Drive - ATAPI Incompatible 5th Master Drive - ATAPI Incompatible 5th Slave Drive - ATAPI Incompatible 6th Master Drive - ATAPI Incompatible 6th Slave Drive - ATAPI Incompatible S.M.A.R.T. Capable but Command Failed S.M.A.R.T.
Error Reporting and Handling Message Displayed Intel® Server Board SE7520JR2 Description when it detects an imminent failure. This message can be reported by an ATAPI device using the S.M.A.R.T. error reporting standard. S.M.A.R.T. failure messages may indicate the need to replace the hard disk. Table 62: Virus Related BIOS Messages Message Displayed BootSector Write !! Description The BIOS has detected software attempting to write to a drive’s boot sector. This is flagged as possible virus activity.
Intel® Server Board SE7520JR2 Error Reporting and Handling Message Displayed Description of channel 2 of the 8254 timer. This may indicate a problem with system hardware. BIOS POST could not initialize the Master Interrupt Controller. This may indicate a problem with system hardware. BIOS POST could not initialize the Slave Interrupt Controller. This may indicate a problem with system hardware.
Error Reporting and Handling Intel® Server Board SE7520JR2 Message Displayed Description bit data structure while the USB is ported with 32-bit data structure. Table 67: SMBIOS BIOS Error Messages Message Displayed Not enough space in Runtime area!!. SMBIOS data will not be available. 6.4.2 Description This message is displayed when the size of the SMBIOS data exceeds the available SMBIOS runtime storage size.
Intel® Server Board SE7520JR2 Error Reporting and Handling Error Code 0012 CMOS time not set Error Message Response Pause 0014 0040 PS2 Mouse not found Refresh timer test failed Not an error Halt 0041 0042 0043 0044 Display memory test failed CMOS Display Type Wrong ~ Pressed DMA Controller Error Pause Pause Pause Halt 0045 DMA-1 Error Halt 0046 DMA-2 Error Halt 0047 0048 Unknown BIOS error.
Error Reporting and Handling Intel® Server Board SE7520JR2 Error Code 8130 8131 8140 8141 8150 8151 8160 8161 8170 8171 8180 8181 8190 8198 8300 8301 8305 84F1 84F2 Error Message Processor 01 disabled Processor 02 disabled Processor 01 failed FRB-3 timer Processor 02 failed FRB-3 timer Processor 01 failed initialization on last boot. Processor 02 failed initialization on last boot.
Intel® Server Board SE7520JR2 Error Reporting and Handling Error code 196 Processor cache mismatch detected. Error messages 198 Processor speed mismatch detected. 00019700 Processor P0 failed BIST. 00019701 Processor P1 failed BIST. 00150100 Multi-bit error occurred: forcing NMI DIMM = ?? 00150100 Multi-bit error occurred: forcing NMI DIMM = ?? DIMM = ?? ( could not isolate) 289 DIMM D?? is Disabled.
Error Reporting and Handling Intel® Server Board SE7520JR2 Table 71: Troubleshooting BIOS Beep Codes Number of Beeps 1, 2 or 3 Troubleshooting Action Reseat the memory, or replace with known good modules. 4-7, 9-11 Fatal error indicating a serious problem with the system. Consult your system manufacturer. Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.
Intel® Server Board SE7520JR2 Error Reporting and Handling Table 73: BMC Beep Code Code Reason for Beep 1 Front panel CMOS clear initiated 1-5-1-1 FRB failure (processor failure) 1-5-2-1 No processors installed or processor socket 1 is empty. 1-5-2-3 Processor configuration error (e.g., mismatched VIDs, Processor slot 1 is empty) 1-5-2-4 Front-side bus select configuration error (e.g., mismatched BSELs) 1-5-4-2 Power fault: DC power unexpectedly lost (e.g.
Error Reporting and Handling Result Amber Intel® Server Board SE7520JR2 Green Red Off MSB LSB Diagnostic LEDs MSB LSB Back edge of baseboard Figure 24. Location of Diagnostic LEDs on Baseboard 6.5.3 POST Code Checkpoints Table 75: POST Code Checkpoints Checkpoint 03 Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB OFF OFF G G 04 OFF G OFF OFF 05 OFF G OFF G Description Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Run-time data area.
Intel® Server Board SE7520JR2 Checkpoint C6 Error Reporting and Handling Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB R A G OFF Description Re-enable cache for boot strap processor C7 R A G G 0A G OFF G OFF 0B G OFF G G 0C G G OFF OFF Detects the presence of Keyboard in KBC port. OFF Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
Error Reporting and Handling Checkpoint 8C Intel® Server Board SE7520JR2 Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB A G OFF OFF 8D A G OFF G 8E A G G OFF 90 R OFF OFF R A0 R OFF R OFF A1 R OFF R G Description Late POST initialization of chipset registers. Build ACPI tables (if ACPI is supported) Program the peripheral parameters. Enable/Disable NMI as selected Late POST initialization of system management interrupt. Check boot password if installed.
Intel® Server Board SE7520JR2 Error Reporting and Handling Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB Checkpoint Description D4 R A OFF R Test base 512KB memory. Adjust policies and cache first 8MB. Set stack. D5 R A OFF A Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. D6 R A G R Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested.
Error Reporting and Handling Intel® Server Board SE7520JR2 Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB Checkpoint Description FA A R A R Check the validity of the recovery file configuration to the current configuration of the flash part. FB A R A A Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.
Intel® Server Board SE7520JR2 6.5.7 Error Reporting and Handling ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events: Table 79: ACPI Runtime Checkpoints Checkpoint 6.5.8 AC Description First ASL check point. Indicates the system is running in ACPI mode. AA System is running in APIC mode.
Error Reporting and Handling 6.
Intel® Server Board SE7520JR2 Connectors and Jumper Blocks 7. Connectors and Jumper Blocks 7.1 Power Connectors The main power supply connection is obtained using a SSI Compliant 2x12 pin connector.
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Table 83: Power Supply Signal Connector (J1G1) Pin 1 Signal 5VSB_SCL Color Orange 2 5VSB_SDA Black 3 PS_ALTER_L, Not used Red 4 3.3V SENSE- Yellow 5 3.3V SENSE+ Green Table 84: IDE Power Connector Pinout (U2E1) Pin 7.
Intel® Server Board SE7520JR2 PinPCI Spec Side Signal B 96 +5V Connectors and Jumper Blocks Description PinSide A PCI Spec Signal Description 96 INTA# This pin will be connected on the 2U riser to INT_A# of the bottom PCI slot, INT_D# of the middle slot and INT_C# of the top slot. This pin will be used by 1U/2U riser to bring the INT_C# interrupt on the bottom PCI slot down to the baseboard.
Connectors and Jumper Blocks PinPCI Spec Side Signal B 62 GND 61 Description IRDY# Intel® Server Board SE7520JR2 PinSide A PCI Spec Signal 62 FRAME# 61 GND Description KEYWAY KEYWAY KEYWAY KEYWAY 60 +3.3V 60 TRDY# 59 DEVSEL# 59 GND 58 PCI-XCAP 58 STOP# 57 LOCK# 57 +3.3V 56 PERR# 56 SMBD Daisy chain to all slots 55 +3.3V 55 SMBCLK Daisy chain to all slots 54 SERR# 54 GND 53 +3.3V 53 PAR /ECC0 52 C/BE[1]# 52 AD[15] 51 AD[14] 51 +3.
Intel® Server Board SE7520JR2 PinPCI Spec Side Signal B 24 AD[57] Connectors and Jumper Blocks Description PinSide A 24 PCI Spec Signal GND 23 GND 23 AD[56] 22 AD[55] 22 AD[54] 21 AD[53] 21 V (I/O) 20 GND 20 AD[52] 19 AD[51] 19 AD[50] 18 AD[49] 18 GND 3.3V or 1.5V Description 17 V (I/O) 17 AD[48] 16 AD[47] 16 AD[46] 15 AD[45] 15 GND 14 GND 14 AD[44] 13 AD[43] 13 AD[42] 12 AD[41] 12 V (I/O) 3.3V or 1.5V 3.3V or 1.
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Table 86: Full-height Riser Slot Pinout Pin-Side B PCI Spec Signal Description Pin-Side A PCI Spec Signal Description 140 12V 140 12V 139 12V 139 12V 138 Ground 138 GND 137 -12V 137 3.3VAux 136 12V 136 Wake# 135 GND 135 12V 134 REFCLK2 + FL-3GIO Slot 2/PXH - DIF5P 134 3.
Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Pin-Side B PCI Spec Signal Description Pin-Side A 101 HSOn(7) 101 GND 100 GND 100 HSIp(7) 99 PCI Spec Signal Description 99 +5V 98 INTB# 98 This pin will be connected on the 2U riser to INT_B# of the bottom PCI slot, INT_A# of the middle slot and INT_D# of the top slot. 97 INTD# This pin will be used by 1U/2U riser to bring the INT_B# interrupt from the top and INT_C# from the middle PCI slot down to the baseboard.
Connectors and Jumper Blocks Pin-Side B PCI Spec Signal Intel® Server Board SE7520JR2 Description Pin-Side A PCI Spec Signal Description 77 +3.3V Was Vio 3.3V or 1.5V 77 GNT1# 76 PME2# active riser only, PME needed per PCI segment, reserved for passive riser 76 Ground 75 AD[31] 75 PME1# for passive slots on both passive and active riser 74 AD[29] 74 PME3# active riser only, PME needed per PCI segment reserved for passive riser 73 Ground 73 AD[30] AD[31] 72 AD[27] 72 +3.
Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Pin-Side B PCI Spec Signal Description Pin-Side A 38 Ground 38 AD[02] 37 AD[01] 37 AD[00] Was Vio 3.3V or 1.5V PCI Spec Signal 36 +3.3V 36 +3.3V 35 ACK64# 35 REQ64# 34 +5V 34 +5V 33 +5V 33 +5V 32 Reserved 32 +5V 31 Ground 31 C/BE[7]# 30 C/BE[6]# 30 C/BE[5]# 29 C/BE[4]# 29 Ground 28 Ground 28 PAR64 27 AD[63] 27 AD[62] 26 AD[61] 26 3.3V 25 3.
Connectors and Jumper Blocks Pin-Side B PCI Spec Signal Description Intel® Server Board SE7520JR2 Pin-Side A PCI Spec Signal Description (2U)01=3x PCI (2U)10=PXH 3 PCI-X-D (2U)11=No Riser 1 Size 7.3 0=1U, 1 = 2U 1 PXH_PWR Input to indicate to PXH on active OK riser that baseboard power is OK System Management Headers The baseboard provides several access points to the management buses built into the baseboard. The following table provides the pinouts for each connector. 7.3.
Intel® Server Board SE7520JR2 FMC Signal Name FML_SINTEX FMC Pin 27 FML_MDA_I2CSDA 28 Connectors and Jumper Blocks Description Fast Management Link Slave Interrupt/Clock Extension. This signal is driven by the FML Slave, and has a dual usage: Used as an Alert signal for the slave to notify master that data is ready to be read from slave Used as a clock Extension (Stretching) for the slave to indicate to the master to extend its low period of the clock Fast Management Link Data Out.
Connectors and Jumper Blocks FMC Signal Name Intel® Server Board SE7520JR2 LAN_I2C_3VSB_SCL FMC Pin 58 Description HDD_FLT_LED_N 64 Drive Fault LED output driven when FMM detects a bad drive from the Hot Swap controller on the Hot Swap disk Drive sub-system. FMM_PS_PWR_ON_N 65 Power On Request to the system Power Supply COOL_FLT_LED_N 66 Cool Fault LED output driven when FMM detects a bad Fan if SSI front panel is detect.
Intel® Server Board SE7520JR2 FMC Signal Name Connectors and Jumper Blocks FMM_RI_BUF_N FMC Pin 97 Description RST_PWRGD_PS 101 Power good signal from power subsystem. In typical system, this signal is connected to PWR_OK signal on power supply. This signal is monitored by the FMM to detect a Power Supply failure LAN_SMBALERT_N 102 Alert signal from the motherboard NIC (LOM). ICH_SLP_S4_N 103 Power Off request from the Chipset ICH_SMI_BUFF_N 105 SMI signal from Chipset.
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Table 89: IPMB Connector Pin-out (J3F1) Pin 1 Signal Name Local I2C SDA 2 GND 3 Local I2C SCL Description BMC IMB 5 V STNDBY Data Line BMC IMB 5 V STNDBY Clock Line Revision 1.
Intel® Server Board SE7520JR2 7.3.4 Connectors and Jumper Blocks OEM RMC Connector (J3B2) A white eight pin connector (J3B2) used for OEM specific management cards. Table 90: OEM RMC Connector Pinout (J3B2) 7.
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Pin A20 GND Signal Name Pin B20 Signal Name FP_PWR_LED_L A21 P5V_STBY B21 RST_IDE_S_L A22 RST_IDE_L B22 FD_HDSEL_L A23 FD_DSKCHG_L B23 FD_RDATA_L A24 FD_WPD_L B24 FD_WDATA_L A25 FD_TRK0_L B25 FD_STEP_L A26 FD_WGATE_L B26 FD_MTR0_L A27 FD_DIR_L B27 FD_DENSEL0 A28 FD_DS0_L B28 FD_INDEX_L A29 GND B29 IDE_SDD_8 A30 IDE_SDD_7 B30 IDE_SDD_9 A31 IDE_SDD_6 B31 IDE_SDD_10 A32 IDE_SDD_5 B32 IDE_SDD_11 A33
Intel® Server Board SE7520JR2 Connectors and Jumper Blocks Pin# 19 Signal Name LAN_ACT_B_L Pin # 20 Signal Name FP_RST_BTN_L 21 PS_I2C_5VSB_SDA 22 GND 23 PS_I2C_5VSB_SCL 24 FP_ID_BTN_L 25 FP_CHASSIS_INTRU 26 TP_J1H5_26 27 LAN_LINKA_L 28 LAN_ACT_A_L 29 GND 30 FP_NMI_BTN_L 31 SPB_EN_L 32 SPB_DSR 33 SPB_SOUT 34 SPB_SIN 35 SPB_CTS_L 36 SPB_RTS_L 37 SPB_DCD_L 38 SPB:DTR_L 39 TEMP_PWM_R 40 VIDEO_IN_USE 41 GND 42 V_IO_VSYNC_BUFF_FP_L 43 GND 44 V_IO_HSYNC_BUFF_FP
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Control Panel Pinout Power LED O O O O O HDD LED O O O O Power Button O O Cool Fault System Fault LAN A Link / A O O Reset Button O O SMBus O O Sleep Button O O O O NMI O O ID LED O O Intruder LAN B Link / A O O ID Button O O O O Figure 25. 34-Pin SSI Compliant Control Panel Header 7.5 7.5.1 I/O Connectors VGA Connector The following table details the pin-out definition of the VGA connector.
Intel® Server Board SE7520JR2 7.5.2 Connectors and Jumper Blocks Pin 12 Signal Name DDCDAT 13 HSYNC (horizontal sync) 14 VSYNC (vertical sync) 15 DDCCLK NIC Connectors The Server Board SE7520JR2 provides two RJ45 NIC connectors oriented side by side on the back edge of the board. The pin-out for each connector is identical and is defined in the following table: Table 95: RJ-45 10/100/1000 NIC Connector Pin-out Pin 1 7.5.
Connectors and Jumper Blocks 7.5.
Intel® Server Board SE7520JR2 7.5.
Connectors and Jumper Blocks Intel® Server Board SE7520JR2 Table 99: Legacy 34-pin Floppy Drive Connector Pin-out (J3K2) 7.5.
Intel® Server Board SE7520JR2 7.5.8 Connectors and Jumper Blocks 3 RXD (receive data) 4 RTS (request to send) 5 TXD (Transmit data) 6 CTS (clear to send) 7 DTR (Data terminal ready) 8 RI (Ring Indicate) 9 Ground Keyboard and Mouse Connector Two stacked PS/2 ports are provided to support both a keyboard and a mouse. Either PS/2 port can support a mouse or keyboard. The following table details the pin-out of the PS/2 connector.
Connectors and Jumper Blocks 4 Intel® Server Board SE7520JR2 GND One internal 1x10 connector on the baseboard (J1F1) provides an option to support an additional two USB 2.0 ports. This connector is used in both the Intel Server Chassis SR1400 1U and SR2400 2U bringing USB support to the control panel. The pin-out of the connector is detailed in the following table.
Intel® Server Board SE7520JR2 Connectors and Jumper Blocks There are two SSI compliant processor fan headers, CPU1 (J7F1) and CPU2 (J5F2), which are not fan speed controlled. They are powered by a constant +12V. The pinout for these two connector is defined in the following table.
Connectors and Jumper Blocks 24 BB_FAN_LED6_R Intel® Server Board SE7520JR2 IN The 1x3 fan header (J3K3) is used to control a system fan in the Intel Server Chassis SR1400. The pinout for this connector is found in the following table. Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3) Pin 1 Signal Name Fan Tach 2 Fan_Speed_Cntl1 Power Power supplied through fan speed control circuitry 3 Ground GND 7.
Intel® Server Board SE7520JR2 7.8 Connectors and Jumper Blocks Jumper Blocks The baseboard has several jumper blocks used to configure or enable/disable various features. This section describes the usage and settings of each. Table 111: Jumper Block Definitions Reference ID J1H2 (A) Name Description CMOS Clear Clears CMOS settings J1H2 (B) BIOS Recovery Boot Forces the system to boot into BIOS Recovery mode. A bootable Recovery BIOS Floppy disk must be in Drive A for this operation.
Design and Environmental Specifications Intel® Server Board SE7520JR2 8. Design and Environmental Specifications 8.1 Server Board SE7520JR2 Design Specification Operation of the Server Board SE7520JR2 at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
Intel® Server Board SE7520JR2 Design and Environmental Specifications Note: The following diagram shows the power harness spec drawing as defined for use in Intel server chassis. Reference chassis designs may or may not require all of the connectors shown and different wiring material may be needed to meet specific platform requirements. P 1 20.0 (0.8") P 4 P 2 30.0 (1.2") P 3 P 7 7 210.0 110 Ref (8.27") (4.3") 400.0 (15.7") 325.0 (12.8") 240.0 (9.45") 100.0 (3.9") 5 8 50 (2") 3 Figure 27.
Design and Environmental Specifications Intel® Server Board SE7520JR2 P1 Main Power Connector • Connector housing: 24-pin Molex* Mini-Fit Jr. 39-01-2245 or equivalent • Contact: Molex Mini-Fit, HCS, female, crimp 44476 or equivalent Table 113: P1 Main Power Connector Pin 1 SIgnal +3.3 VDC 18 AWG Color Orange Pin 13 SIgnal +3.3 VDC 18 AWG Color Orange 2 +3.
Intel® Server Board SE7520JR2 Design and Environmental Specifications P3 Power Signal Connector • Connector housing: 5-pin Molex 50-57-9705 or equivalent • Contacts: Molex 16-02-0087 or equivalent Table 115: P3 Baseboard Signal Connector Pin 1 SIgnal I2C Clock 24 AWG Color White/Green Stripe 2 I2C Data White/Yellow Stripe 3 Alert# White 4 COM Black 5 3.
Design and Environmental Specifications Intel® Server Board SE7520JR2 enclosure). This grounding must be designed to ensure passing the maximum allowed Common Mode Noise levels. The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 mΩ. This path may be used to carry DC current. 8.2.
Intel® Server Board SE7520JR2 8.2.5 Design and Environmental Specifications Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. All outputs are measured with reference to the return remote sense signal (ReturnS). The 5V, 12V1, 12V2, +12V3, –12V and 5VSB outputs are measured at the power supply connectors referenced to ReturnS. The +3.
Design and Environmental Specifications 8.2.7 Intel® Server Board SE7520JR2 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges. Table 120: Capacitve Loading Conditions 8.2.8 Output +3.
Intel® Server Board SE7520JR2 8.2.11 Design and Environmental Specifications Soft Starting The power supply shall contain control circuit that provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5V Standby but the turn on/off shall be monotonic. 8.2.
Design and Environmental Specifications Intel® Server Board SE7520JR2 Vout V1 10% Vout V2 V3 V4 Tvout Tvout_off rise Tvout_on Figure 28. Output Voltage Timing Table 123: Turn On/Off Timing Item Tsb_on_delay Description Delay from AC being applied to 5VSB being within regulation. Minimum Maximum 1500 Units msec T ac_on_delay Delay from AC being applied to all output voltages being within regulation.
Intel® Server Board SE7520JR2 Design and Environmental Specifications AC Input Tvout_holdup Vout Tpwok_low TAC_on_delay Tsb_on_delay Tpwok_on PWOK Tpwok_off Tsb_on_delay Tpwok_on Tpwok_holdup 5VSB Tsb_vout Tpwok_off Tpson_pwok T5VSB_holdup Tpson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 29. Turn On/Off Timing (Power Supply Signals) 8.2.
Design and Environmental Specifications 8.3 Intel® Server Board SE7520JR2 Product Regulatory Compliance 8.3.
Intel® Server Board SE7520JR2 8.3.
Design and Environmental Specifications 8.4 Intel® Server Board SE7520JR2 Electromagnetic Compatibility Notices 8.4.1 FCC (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E.
Intel® Server Board SE7520JR2 Design and Environmental Specifications This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled: “Digital Apparatus,” ICES-003 of the Canadian Department of Communications. 8.4.3 Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC).
Miscellaneous Board Information Intel® Server Board SE7520JR2 9. Miscellaneous Board Information 9.1 Updating the System Software To ensure your Server Board SE7520JR2 has the latest board fixes, it is highly recommended to load the latest system software. These include System BIOS, mBMC firmware, and FRUSDR Utility.
Intel® Server Board SE7520JR2 • Miscellaneous Board Information Replacing a bad baseboard Adding/Removing a Redundancy Feature (IMM Systems Only) o Redundant Power Supplies o Redundant Fans Adding/Removing a CPU fan (IMM Systems Only) • • Failure to run the FRUSDR Update Utility may cause the platform management sub-system to report false errors causing your platform to operate erratically.
Miscellaneous Board Information Intel® Server Board SE7520JR2 Clear state and power the system up. This feature can be enabled or disabled via the CMOS Clear Options command. The following sequence of events must occur to invoke the Control Panel CMOS Clear feature. 1. Standby power must be on, system power must be off, and the feature enabled. 2. The control panel reset button must be pressed and held for at least 4 seconds 3.
Intel® Server Board SE7520JR2 • • • Miscellaneous Board Information Recovery from multiple floppy disks. o Prepare 2 blank disks. o The first disk(disk0) must be made bootable o Copy amiboot.000 to disk0, and amiboot.001 to disk1. Execute BIOS Recovery o set Recovery Boot Jumper by moving jumper J1H2 row B from Pins 1-2 to Pins 2-3 o Insert the recovery media to the appropriate drive or USB interface.
Intel® Server Board SE7520JR2 Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips The following Integration and Usage Tips are provided to assist with answering miscellaneous questions about the Server Board SE7520JR2 or as a guide to assist with troubleshooting common errors. • • • • • • • • The use of DDR2 - 400 MHz or DDR - 266/333 MHz DIMMs is dependant on which board SKU is used. DDR-2 DIMMs cannot be used on a board designed to support DDR.
Glossary Intel® Server Board SE7520JR2 Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
Intel® Server Board SE7520JR2 Glossary Term Definition IFB I/O and firmware bridge IMM Intel Management Module INTR IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-target probe KB 1024 bytes.
Glossary Intel® Server Board SE7520JR2 Term SEEPROM Definition Serial electrically erasable programmable read-only memory SEL System Event Log SIO Server Input/output SMI Server management interrupt. SMI is the highest priority nonmaskable interrupt. SMM Server management mode. SMS Server management software SNMP Simple Network Management Protocol. TBD To Be Determined TBSG TIM Thermal Interface Material UART universal asynchronous receiver/transmitter UDP User Datagram Protocol.
Intel® Server Board SE7520JR2 Reference Documents Reference Documents Refer to the following documents for additional information: • • • • • • • • • • • • • • Intel® Server Board SE7520JR2 Server Management External Architecture Specification (EAS). Intel Corporation. Intel® Server Board SE7520JR2 BIOS External Product Specification. Intel Corporation Intel® Server Board SE7520JR2 BMC External Product Specification.
