Technical Product Specification

Power Sub-system Intel® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
40
Table 35. Voltage Regulation Limits
Parameter Tolerance MIN NOM MAX Units
+ 12V - 5% / +5% +11.40 +12.00 +12.60 V
rms
+ 5VSB - 5% / +5% +4.75 +5.00 +5.25 V
rms
2.2.3.7 Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading
presented in the following table. The load transient repetition rate was tested between 5 Hz and
5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere between the MIN load and MAX load
defined in the following table.
Table 36. Transient Load Requirements
Output Max Δ Step Load Size Max Load Slew Rate Test Capacitive Load
12 V 32.0 A
1
0.5 A/μs 2200 μF
+5 VSB 0.5 A 0.5 A/μs 20 μF
Notes:
1. Step loads on each 12V output may happen simultaneously.
2. The +12V should be tested with 2200
μF evenly split between the three +12V rails.
2.2.3.8 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges. Minimum capacitive loading applies to static load only.
Table 37. Capacitive Loading Conditions
Output MIN MAX Units
+12V 2000 11,000
μF
+5VSB 1 350
μF
2.2.3.9 Closed Loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions, including
capacitive load ranges. A minimum 45-degree phase margin and -10dB-gain margin is met.
Closed-loop stability is ensured at the maximum and minimum loads, as applicable.
2.2.3.10 Common Mode Noise
The Common Mode Noise on any output does not exceed 350mV pk-pk over the frequency
band of 10 Hz to 20 MHz.