Technical Product Specification

Power Sub-system Intel® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
102
Signal Type Accepts an open collector/drain input from the system. Pull-up
to 5 V located in power supply.
PSON
#
= Low ON
PSON
#
= High or Open OFF
MIN MAX
Logic level low (power supply ON) 0V 1.0V
Logic level high (power supply OFF) 2.0V 5.25V
Source current, Vpson = low 4mA
Power up delay: T
pson_on_delay
5 msec 400 msec
PWOK delay: T
pson_pwok
50 msec
Figure 25. PSON# Required Signal Characteristics
2.5.7.2 PWOK (Power OK) Output Signal
PWOK is a power OK signal and is pulled HIGH by the power supply to indicate all the outputs
are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power is removed for a time sufficiently long so the power supply
operation is no longer guaranteed, PWOK is de-asserted to a LOW state. The start of the
PWOK delay time is inhibited as long as any power supply output is within current limit.
Table 120. PWOK Signal Characteristics
Signal Type Open collector/drain output from power supply. Pull-up to VSB
located in system.
PWOK = High Power OK
PWOK = Low Power Not OK
MIN MAX
Logic level low voltage, Isink=4mA 0 V 0.4 V
Logic level high voltage, Isource=200μA
2.4 V 5.25 V
Sink current, PWOK = low 4m A
Source current, PWOK = high 2m A
≤ 1.0 V
PS is
enabled
≥ 2.0 V
PS is
disabled
1.0V
4.
.0V
Enabled
Disabled
0.3V ≤ Hysterisis ≤ 1.0V
In 1.0-2.0V input voltages range is required
5.
.25V
6.
V