Technical Product Specification

Intel® Server Chassis SC5650 TPS Power Sub-system
Revision 1.2
Intel order number E39531-004
97
Table 113. Transient Load Requirements
Output Δ Step Load Size
(See note 2)
Load Slew Rate Test capacitive Load
+3.3V 6.0A
0.25 A/μsec 970 μF
+5V 4.0A
0.25 A/μsec 400 μF
12V1+12V2 18.0A
0.25 A/μsec 2200 μF 1,2
+5VSB 0.5A
0.25 A/μsec 20 μF
Notes
1) Step loads on each 12V output may happen simultaneously.
2) The +12V should be tested with 2200μF evenly split between the four +12V rails
3) +5V/3.5A,+12V/30A and +5V/8A,+12V/5A load combination will be used for cross load regulation.
2.5.5.7 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
Table 114. Capacitive Loading Conditions
Output MIN MAX Units
+3.3V 250 5000
μF
+5V 400 5000
μF
+12V 500 8000
μF
-12V 1 350
μF
+5VSB 20 350
μF
2.5.5.8 Closed Loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions including
capacitive load ranges in Section 2.5.5.7. A minimum of a 45-degree phase margin and -10dB-
gain margin is required. The power supply manufacturer provides proof of the unit’s closed-loop
stability with local sensing through the submission of Bode plots. Closed-loop stability is
ensured at the maximum and minimum loads as applicable.
2.5.5.9 Residual Voltage Immunity in Standby Mode
The power supply is immune to any residual voltage placed on its outputs (typically a leakage
voltage through the system from standby output) up to 500mV. There is neither additional heat
generated nor stressing of any internal components with this voltage applied to any individual
output or all outputs simultaneously. Residual voltage also does not trip the protection circuits
during turn on/off.
The residual voltage at the power supply outputs for a no-load condition does not exceed
100 mV when AC voltage is applied.