Technical Product Specification

Power Sub-system Intel® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
62
Signal Type Accepts an open collector/drain input from the system. Pull-up
to VSB located in power supply.
PSON
#
= Low ON
PSON
#
= High or Open OFF
MIN MAX
Logic level low (power supply ON) 0V 1.0V
Logic level high (power supply OFF) 2.0V 5.25V
Source current, Vpson = low 4mA
Power up delay: T
pson_on_delay
5msec 400msec
PWOK delay: T
pson_pwok
50msec
2.3.4.2 PSKILL
The purpose of the PSKill pin is to allow for hot swapping of the power supply. The mating pin of
this signal on the cage input connector is tied to ground, and its resistance is less than 5 ohms.
2.3.4.3 PWOK (Power OK) Input and Output Signals
PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits, or when AC power has been removed for a time sufficiently long so that power
supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. The start
of the PWOK delay time is inhibited as long as any power supply output is within current limit.
Table 66. PWOK Signal Characteristics
Signal Type Open collector/drain output from power supply. Pull-up to VSB
located in system.
PWOK = High Power OK
PWOK = Low Power Not OK
MIN MAX
Logic level low voltage, Isink=4mA 0V 0.4V
Logic level high voltage, Isource=200μA
2.4V 5.25V
Sink current, PWOK = low 4mA
Source current, PWOK = high 2mA
PWOK delay: T
pwok_on
100ms 1000ms
PWOK rise and fall time
100μsec
Power down delay: T
pwok_off
1ms 200msec
2.3.4.4 SMBAlert#
The SMBAlert# signal indicates that the power supply is experiencing a problem that the user
should investigate. The signal may be asserted due to critical events or warning events.
The SMBAlert# signal will be asserted whenever there is at least one event condition in the
power supply or cage.