Technical Product Specification

Power Sub-system IntelĀ® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
58
2.3.2.11 Timing Requirements
The timing requirements for the power supply/PDB combination are as follows. The output
voltages must rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70 ms, except for
5VSB, which is allowed to rise from 1.0 to 25 ms. The +3.3V, +5V, and +12V output voltages
start to rise at approximately the same time. All outputs rise monotonically. The +5V output is
greater than the +3.3V output during any point of the voltage rise. The +5V output is never
greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation
within 50ms (T
vout_on
) of each other during turn on of the power supply. Each output voltage falls
out of regulation within 400 msec (T
vout_off
) of each other during turn off. The following figure
shows the timing requirements for the power supply being turned on and off via the AC input,
with PSON held low and the PSON signal, with the AC input applied.
Table 61. Output Voltage Timing
Item Description Minimum Maximum Units
T
vout_rise
Output voltage rise time from each main output. 5.0* 70* msec
T
vout_on
All main outputs must be within regulation of each
other within this time.
50 msec
T
vout_off
All main outputs must leave regulation within this
time.
400 msec
* The 5VSB output voltage rise time shall be from 1.0 ms to 25.0 ms.
Figure 15. Output Voltage Timing
Vout
10%
Vout
T
vout rise
T
vout_on
T
vout_off
V1
V2
V3
V4