Technical Product Specification

Power Sub-system Intel® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
42
Figure 12. Output Voltage Timing
Table 40. Turn On / Off Timing
Item Description Minimum Maximum Units
T
sb_on_delay
Delay from AC being applied to 5 VSB being within
regulation.
1500
ms
T
ac_on_delay
Delay from AC being applied to all output voltages being
within regulation.
2500
ms
T
vout_holdup
Time all output voltages stay within regulation after loss of
AC.
21
ms
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK 20 ms
T
pson_on_delay
Delay from PSON
#
active to output voltages within regulation
limits.
5 400
ms
T
pson_pwok
Delay from PSON
#
deactive to PWOK being de-asserted. 50 ms
T
pwok_on
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
100 1000
ms
T
pwok_off
Delay from PWOK de-asserted to 12-V output voltage
dropping out of regulation limits.
1
ms
T
pwok_low
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal.
100
ms
T
sb_vout
Delay from 5 VSB being in regulation to O/Ps being in
regulation at AC turn on.
50 1000
ms
T
5VSB_holdup
Time the 5 VSB output voltage stays within regulation after
loss of AC.
70
ms
Note:
1 T
vout_holdup
and T
pwok_holdup
are defined under 75% loading.
Vout
10%
Vout
T
vout rise
T
vout_on
T
vout_off
V1
V2
V3
V4