Technical Product Specification
Intel® Server Chassis SC5650 TPS Power Sub-system
Revision 1.2
Intel order number E39531-004
41
2.2.3.11 Ripple / Noise
The maximum ripple/noise output of the power supply is defined in the following table. This is
measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A 10μF
tantalum capacitor in parallel with a 0.1μF ceramic capacitor is placed at the point of
measurement.
Table 38. Ripple and Noise
+12V Output +5VSB Output
120mVp-p 50mVp-p
2.2.3.12 Forced Load Sharing
The +12V output has forced load sharing. The output shares within 10% at full load. All current
sharing functions are implemented internal to the power supply by making use of the 12LS
signal. The power distribution board connects the 12LS signal between the two power supplies.
The failure of a power supply does not affect the load sharing or output voltages of the other
supplies still operating. The supplies are able to load share with up to two power supplies in
parallel and can operate in a hot-swap / redundant 1+1 configuration. The 5Vsb output is not
required to actively share current between power supplies (passive sharing). The 5Vsb outputs
of the power supplies are connected together in the system so that a failure or hot swap of a
redundant power supply does not cause these outputs to go out of regulation in the system.
2.2.3.13 Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70 ms except for 5VSB, which is
allowed to rise from 1.0 to 25 ms. All outputs rise monotonically. The following figure shows the
timing requirements for the power supply being turned on and off via the AC input, with PSON
held low and the PSON signal with the AC input applied.
Table 39. Output Voltage Timing
Item Description Minimum Maximum Units
T
vout_rise
Output voltage rise time from each main output. 5.0* 70* msec
T
vout_on
All main outputs must be within regulation of each
other within this time.
50 msec
T
vout_off
All main outputs must leave regulation within this
time.
400 msec
• The 5VSB output voltage rise time should be from 1.0 ms to 25.0 ms.