Technical Product Specification
Power Sub-system Intel® Server Chassis SC5650 TPS
Revision 1.2
Intel order number E39531-004
24
2.1.5.11 Common Mode Noise
The Common Mode noise on any output does not exceed 350mV pk-pk over the frequency
band of 10Hz to 30MHz.The measurement is made across a 100Ω resistor between each of the
DC outputs including ground at the DC power connector and chassis ground (power subsystem
enclosure). The test set-up uses an FET probe, such as a Tektronix* P6046, or equivalent.
2.1.5.12 Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 10 Hz to 20 MHz at the power supply output connectors.
A 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor is placed at the point of
measurement.
Table 18. Ripple and Noise
+3.3V +5V +12V(1,2,3,4) -12V +5VSB
50mVp-p 50mVp-p 120mVp-p 120mVp-p 50mVp-p
2.1.5.13 Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70ms, except for 5VSB which is
allowed to rise from 1.0 to 25ms. The +3.3V, +5V and +12V output voltages start to rise at
approximately the same time. All outputs must rise monotonically. The 5V output must be
greater than the +3.3V output during any point of the voltage rise. The +5V output must never
be greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation
within 50 ms (T
vout_on
) of each other during turn on of the power supply. Each output voltage falls
out of regulation within 400msec (T
vout_off
) of each other during turn off. The following table
shows the timing requirements for the power supply being turned on and off via the AC input
with PSON held low and the PSON signal with the AC input applied.
Table 19. Output Voltage Timing
Item Description Minimum Maximum Units
T
vout_rise
Output voltage rise time from each main output. 5.0* 70* msec
T
vout_on
All main outputs must be within regulation of each
other within this time.
50 msec
T
vout_off
All main outputs must leave regulation within this
time.
400 msec
• The 5VSB output voltage rise time should be from 1.0 ms to 25 ms.