Technical Product Specification

Functional Architecture Intel® Server Board S5520UR and S5520URT TPS

Intel order number E44031-012 Revision 1.9

 If both processor sockets are populated, the next upgrade from the Single Channel

mode installs DIMM_D1. This configuration results in an optimal memory thermal spread,

as well as Non-Uniform Memory Architecture (NUMA) aware interleaving. The BIOS

selects the Independent Channel mode of operation.

 If only one processor socket is populated, the next upgrade from the Single Channel

mode is installing DIMM_B1 to allow channel interleaving. The system operates in the

Independent Channel mode.

 The DIMM parameter-matching requirements for memory RAS is local to a socket.

For

example, while Channels A/B/C can have one match of timing, technology, and size,

Channels D/E/F can have a different set of parameters and RAS still functions.

 DDR3 DIMMs on adjacent slots on the same channel do not need to be identical.

 For the Mirrored Channel mode, the memory in Channels A and B of Socket 1 must be

identical and Channel C should be empty. Similarly, the memory in Channels D and E of

Socket 2 must be identical and Channel F should be empty.

a. The minimum population upgrade for the Mirrored Channel mode is DIMM_A1,

DIMM_B1, DIMM_D1, and DIMM_E1 with both processor sockets populated.

DIMM_A1 and DIMM_B1 as a pair must be identical, and so must DIMM_D1 and

DIMM_E1, but the DIMMs on different processor sockets do not need to be identical.

Failing to comply with these rules results in a switch back to the Independent

Channel mode.

b. If Mirrored Channel mode is selected and the third channel of each processor socket

is not empty, the BIOS disables the memory in the third channel of each processor

socket.

 In the Mirrored Channel mode, both sockets must simultaneously satisfy the DIMM

matching rules on their respective adjacent channels. If the DDR3 DIMMs on adjacent

channels of a socket are not identical, the BIOS configures both the processor sockets

to default to the Independent Channel mode. If DIMM_D1 and DIMM_E1 are not

identical, then the system switches to the Independent Channel Mode