Technical Product Specification

Intel® Server Board S5520UR and S5520URT TPS Functional Architecture
Revision 1.9 Intel order number E44031-012
29
3.2.5 Memory Upgrade Rules
Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the
following factors:
 Current RAS mode of operation
 Existing DDR3 DIMM population
 DDR3 DIMM characteristics
 Optimization techniques used by the Intel
®
Xeon
®
Processor 5500 Series and Intel
®
Xeon
®
Processor 5600 Series to maximize memory bandwidth
In the Channel Independent mode, all DDR3 channels operate independently. The Channel
Independent mode can also be used to support a single DIMM configuration in channel A and in
the single channel mode.
The following general rules must be observed when selecting and configuring memory to obtain
the best performance from the system.
 Mixing RDIMMs and UDIMMs is not supported.
 If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during
memory initialization and is (essentially) disabled by the BIOS. If a DDR3 DIMM has no
or missing SPD information, the slot in which it is placed is treated as empty by the
BIOS.
 When CPU Socket 1 is empty, any DIMM memory in Channel A through Channel C is
unavailable.
 When CPU Socket 2 is empty, any DIMM memory in Channel D through Channel F is
unavailable.
 If both processor sockets are populated but Channel A through Channel C is empty, the
platform can still function with remote memory in Channel D through Channel F.
However, platform performance suffers latency due to remote memory.
 The memory operational mode is configurable at the channel level. Two modes are
supported: Independent Channel and Mirrored Channel.
 The memory slots of each DDR3 channel from the Intel
®
Xeon
®
Processor 5500 Series
and Intel
®
Xeon
®
Processor 5600 Series are populated on a farthest first fashion. This
holds true even for the Independent Channel mode. Therefore, if A1 is empty, A2
cannot be populated or used.
 The BIOS selects Independent Channel mode by default, which enables all installed
memory on all channels simultaneously.
 Mirrored Channel mode is not available when only one processor is populated (CPU
Socket 1).
 If both processor sockets are populated and the installed DIMMs are associated with
both processor sockets, then a given RAS mode is selected only if both the processor
sockets are populated to conform to that mode.
 The minimum memory population possible is one DIMM in slot A1. In this configuration,
the system operates in the Independent Channel mode. RAS is not available.