Technical Product Specification

ManualsBrandsIntel ManualsOtherIntel Server Board S5520UR

Functional Architecture Intel® Server Board S5520UR and S5520URT TPS

Intel order number E44031-012 Revision 1.9

3.2.4 Memory RAS

3.2.4.1 RAS Features

The server board supports the following memory RAS features:

 Channel Independent Mode

 Channel Mirroring Mode

The memory RAS offered by the Intel

Xeon

Processor 5500 Series and Intel

Xeon

Processor 5600 Series is done at channel level, i.e., during mirroring, channel B mirrors

channel A. All DIMM matching requirements are on a slot to slot basis on adjacent channels.

For example, to enable mirroring, corresponding slots on channel A and channel B must have

DIMMS of identical parameters. But DIMMs on adjacent slots on the same channel do not need

identical parameters.

If one socket fails the population requirements for RAS, the BIOS sets all six channels to the

Channel Independent mode. One exception to this rule is when all DIMM slots from a socket

are empty. E.g., when only sockets A1, B1, C1 are populated, mirroring is possible on the

platform.

The memory slots of DDR3 channels from the Intel

Xeon

Processor 5500 Series and Intel

Xeon

Processor 5600 Series should be populated on a farthest first fashion. This holds true

even in the Channel Independent mode. This means that A2 cannot be populated or used if A1

is empty.

3.2.4.2 Channel Independent Mode

In the Channel Independent mode, multiple channels can be populated in any order (e.g.,

channels B and C can be populated while channel A is empty). Also, DIMMs on adjacent

channels need not have identical parameters. Therefore, all DIMMs are enabled and utilized in

the Channel Independent mode.

Adjacent slots on a DDR3 channel from The Intel

Xeon

Processor 5500 Series and Intel

Xeon

Processor 5600 Series do not need matching size and organization. However the speed

of the channel is configured to the maximum common speed of the DIMMs.

The single channel mode is established using the Channel Independent mode by populating

DIMM slots from channel A only.

3.2.4.3 Channel Mirroring Mode

The Intel

Xeon

Processor 5500 Series and Intel

Xeon

Processor 5600 Series support

channel mirroring to configure available channels of DDR3 DIMMS in the mirrored configuration.

Unlike channel sparing, the mirrored configuration is a redundant image of the memory, and

can continue to operate despite the presence of sporadic uncorrectable errors.

Channel mirroring is a RAS feature in which two identical images of memory data are

maintained, thus providing maximum redundancy. On the Intel

Xeon

Processor 5500 Series

and Intel

Xeon

Processor 5600 Series-based Intel

server boards, mirroring is achieved

across channels. Active channels hold the primary image and the other channels hold the

secondary image of the system memory. The integrated memory controller in the Intel

Xeon