Technical Product Specification

Intel® Server Board S5520UR and S5520URT TPS Functional Architecture
Revision 1.9 Intel order number E44031-012
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3.2.3 Publishing System Memory
 The BIOS displays the Total Memory of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in
the system.
 The BIOS displays the Effective Memory of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled)
and not used as redundant units.
 The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.
 If Display Logo is disabled, the BIOS displays the total system memory on the
diagnostic screen at the end of POST. This total is the same as the amount described
by the first bullet above.
 Memory Map and Population Rules
The nomenclature for DIMM sockets implemented on the Intel
®
Server Board S5520UR,
S5520URT is detailed in the following table:
Table 7. DIMM Nomenclature
Processor Socket 1
Processor Socket 2
Channel A Channel B Channel C Channel D Channel E Channel F
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
3.2.3.1 Memory Subsystem Nomenclature
 DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
 The memory channels from processor socket 1 are identified as Channel A, B, and C.
The memory channels from processor socket 2 are identified as Channel D, E, and F.
 The silk screened DIMM slot identifiers on the board provide information about the
channel, and therefore the processor to which they belong. For example, DIMM_A1 is
the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on
Channel D on processor 2.
 The memory slots associated with a given processor are unavailable if the given
processor socket is not populated.
 A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory.
In this case, the memory is
shared by the processors.
However, the platform suffers performance degradation and
latency due to the remote memory.
 Processor sockets are self-contained and autonomous. However, all memory subsystem
support (such as Memory RAS, Error Management,) in the BIOS setup are applied
commonly across processor sockets.