Technical Product Specification

Functional Architecture Intel® Server Board S5520UR and S5520URT TPS
Intel order number E44031-012 Revision 1.9
24
DIMM Type
DIMM
Populated Per
Channel
Memory Running Frequency
(Y/N)
Command/Addre
ss Rate
Ranks Per DIMM
SR: Single-Rank
DR: Dual-Rank
QR: Quad-Rank
Description
800MHz
1066MHz
1333MHz
1.35V
w/ECC
installed memory: 800 MHz, 1066 MHz
RDIMM
DDR3L
1.35V
w/ECC
2 Y N N 1N
Mixing SR , DR ,
QR
All RDIMMs run at the fastest common
frequency of processor IMCs and
installed memory: 800 MHz
UDIMM 1.5V
w or w/o
ECC
1 Y Y Y 1N SR or DR
All UDIMMs run at the fastest common
frequency of processor IMCs and
installed memory: 800 MHz, 1066 MHz,
or 1333 MHz(2 DIMMs Populated per
Channel at 1333 MT/s is only supported
on UDIMMs with ECC support)
UDIMM 1.5V
w or w/o
ECC
2 Y Y Y 2N Mixing SR , DR
All UDIMMs run at the fastest common
frequency of processor IMCs and
installed memory: 800 MHz, 1066 MHz,
or 1333 MHz(2 DIMMs Populated per
Channel at 1333 MT/s is only supported
on UDIMMs with ECC support)
UDIMM
1.35V
w/ECC
1 Y Y Y 1N SR or DR
All UDIMMs run at the fastest common
frequency of processor IMCs and
installed memory: 800 MHz, 1066 MHz,
or 1333 MHz
UDIMM
1.35V
w/ECC
2 Y Y N 2N Mixing SR , DR
All UDIMMs run at the fastest common
frequency of processor IMCs and
installed memory: 800 MHz, 1066 MHz,
Notes:
1. One clock cycle for the DRAM commands arrive at the DIMMs to execute.
2. Two clock cycles for the DRAM commands arrive at the DIMMs to execute.