Technical Product Specification

Intel® Server Board S5520UR and S5520URT TPS Design and Environmental Specifications
Revision 1.9 Intel order number E44031-012
129
Table 77. Transient Load Requirements
Output
 Step Load Size
(See note 2)
Load Slew Rate
Test capacitive Load
+3.3 V
5.0 A
0.25 A/
µ
sec
250
µ
F
+5 V
6.0 A
0.25 A/
µ
sec
400
µ
F
12 V1 + 12 V2 +
12 V3 + 12 V4
28.0 A
0.25 A/µsec 2200 µF
1,2
+5 VSB
0.5 A
0.25 A/
µ
sec
20
µ
F
Notes:
1. Step loads on each 12 V output may happen simultaneously.
2. The +12 V should be tested with 2200 µF evenly split between the four +12 V rails.
9.3.6 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive
loading ranges.
Table 78. Capacitve Loading Conditions
Output
Minimum
Maximum
Units
+3.3 V 100 6,800
µF
+5 V
10
4,700
µF
+12 V1,2,3,4
220 each
11,000
µF
-12 V
1
350
µF
+5 VSB
20
2000
µF
9.3.7 Closed-loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions including
capacitive load ranges.
A minimum of 45 degrees phase margin and -10 dB-gain margin is
required.
The power supply manufacturer provides proof of the unit’s closed-loop stability with
local sensing through the submission of Bode plots.
Closed-loop stability is ensured at the
maximum and minimum loads as applicable.