Technical Product Specification

Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs
Revision 1.9 Intel order number E44031-012
111
Table 66. RiserType and PEWIDTH Mapping
IOH
Strapping
PEWIDTH[5]
PEWIDTH[4]
PEWIDTH[3]
PEWIDTH[2]
PEWIDTH[1]
PEWIDTH[0]
Riser/Server
board
(Server board)
RiserType[3]
RiserType[2]
RiserType[1]
(Server board)
RiserType[0]
PEWIDTH[5] is pulled high by the server board while PEWIDTH[1] is controlled by the I/O
expansion module.
6.7.2.1 Strapping Option
Intel
®
Server Board S5520UR, S5520URT risers support a pull-down resistor strapping option
for each of the four RiserType pins.
The pull-up resistors are not required on the riser as they
are located on the server board.
A strong resistor value of 100 ohms or less is recommended
on the riser.
6.7.3 PCI Express* Trace Length Consideration
PCI Express* Gen2 lanes have a maximum trace length requirement that is considerably
shorter than for Gen1.
Given the significant differences in trace lengths on the server board,
Intel
®
Server Board S5520UR, S5520URT risers have the IOH port assigned to the PCI
Express* slot that
minimizes any one lane going beyond the maximum trace length specification.
The following table provides the trace lengths from the IOH to the riser slot.
Given that the trace
length varies from a minimum of 4.5 inches to maximum of 7.8 inches on the server board,
traces on any riser card need to be routed to keep the maximum length under the specification.
Table 67. Trace Lengths
Server board (IOH)
Netnames
Length (inches)
PE3
P2E_IOH_SLOT6_[7:4]
4.5
PE4
P2E_IOH_SLOT6_[3:0]
5.0
PE5
P2E_IOH_SLOT5_[7:4]
5.7
PE6
P2E_IOH_SLOT
5
_[3:0]
6.7
PE7
P2E_IOH_SLOT4_[7:4]
7.4
PE8
P2E_IOH_SLOT4_[3:0]
7.8
6.7.4 Reference Clocks
Seven 100-MHz reference clocks are provided to the riser from the DB1200 Clock Buffer on the
server board.
These clocks can be used for PCI Express* slots or various devices such as PCI
Express* packet switches and PCI Express* to PCI-X bridges.
As these clocks are kept enabled
by default, there are no rules for assigning the IOH PCI Express* port to Clock to Slot.
Any of
the clocks can be used in the design.
6.7.5 Power Budget
The Power Rail pins have been defined with the maximum current per rail as mentioned in the
following table.