Technical Product Specification

Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS
Intel order number E44031-012 Revision 1.9
110
Table 65. Port Bifurcation Control
PEWIDTH[5:0]
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
11111
Wait-on-BIOS
100000 x4 Not
present
x4 x4 X4 x4 x4 x4 x4 x4
100001 x4 Not
present
x4 x4 X4 x4 x8 Not
present
x4 x4
100010
x4
Not
present
x4
x4
X4
x4
x4
x4
x8
Not
present
100011
x4
Not
present
x4
x4
X4
x4
X8
Not
present
x8
Not
present
100100
x4
Not
present
x8
Not
present
X4
x4
x4
x4
x4
x4
100101
x4
Not
present
x8
Not
present
X4
x4
X8
Not
present
x4
x4
100110
x4
Not
present
x8
Not
present
X4
x4
x4
x4
x8
Not
present
100111
x4
Not
present
x8
Not
present
X4
x4
X8
Not
present
x8
Not
present
101000 x4 Not
present
x4 x4 X8 Not
present
x4 x4 x4 x4
101001 x4 Not
present
x4 x4 X8 Not
present
X8 Not
present
x4 x4
101010
x4
Not
present
x4
x4
X8
Not
present
x4
x4
x8
Not
present
101011
x4
Not
present
x4
x4
X8
Not
present
X8
Not
present
x8
Not
present
101100
x4
Not
present
x8
Not
present
X8
Not
present
x4
x4
x4
x4
101101
x4
Not
present
x8
Not
present
X8
Not
present
X8
Not
present
x4
x4
101110
x4
Not
present
x8
Not
present
X8
Not
present
x4
x4
x8
Not
present
101111
x4
Not
present
x8
Not
present
X8
Not
present
X8
Not
present
x8
Not
present
110000
x4
Not
present
x16
Not
present
Not
present
Not
present
x4
x4
x4
x4
110001 x4 Not
present
x16 Not
present
Not
present
Not
present
X8 Not
present
x4 x4
110010
x4
Not
present
x16
Not
present
Not
present
Not
present
x4
x4
x8
Not
present
110011
x4
Not
present
x16
Not
present
Not
present
Not
present
X8
Not
present
x8
Not
present
See Table 9 in Section 3.4.1 for the port mapping on Intel
®
Server Board S5520UR ,
S5520URT
Although the PEWIDTH contains a total of six bits, only four are routed to the riser. The
following table shows the mapping of RiserType[3:0] pins to PEWIDTH[5:0].