Technical Product Specification

Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs
Revision 1.9 Intel order number E44031-012
109
Table 64. PCI Express* Port Bifurcation
Intel
®
ICH10
Signal Type
Signal Name
Description
PE1
PE1RN[3:0], PE1RP[3:0], PE1TN[3:0],
PE1TP[3:0]
x4
PE2
PE2RN[3:0], PE2RP[3:0], PE2TN[3:0],
PE2TP[3:0]
PE3 PE3RN[3:0], PE3RP[3:0], PE3TN[3:0],
PE3TP[3:0]
X8 X16
PE4 PE4RN[3:0], PE4RP[3:0], PE4TN[3:0],
PE4TP[3:0]
PE5
PE5RN[3:0], PE5RP[3:0], PE5TN[3:0],
PE5TP[3:0]
X8
PE6
PE6RN[3:0], PE6RP[3:0], PE6TN[3:0],
PE6TP[3:0]
PE7
PE7RN[3:0], PE7RP[3:0], PE7TN[3:0],
PE7TP[3:0]
X8
X16
PE8
PE8RN[1:0], PE8RP[1:0], PE8TN[1:0],
PE8TP[1:0]
PE9
PE9RN[1:0], PE9RP[1:0], PE9TN[1:0],
PE9TP[1:0]
X8
PE10
PE10RN[1:0], PE10RP[1:0],
PE10TN[1:0], PE10TP[1:0]
DMI
DMIRN[3:0], DMIRP[3:0], DMITN[3:0],
DMITP[3:0]
Not Combinable
Common Signals PE{0/1}CLKN, PE{0/1}CLKP, VCCAPE,
VSS, PE{0/1}ICOMPI,
PE{0/1}RCOMPO, VCCAPEBG,
VSSAPEBG
Common Signals
6.7.2 ‘Riser Type’ Signals
The riser connector pin-out contains four Riser Type (or Riser ID) pins. These signals are part
of the IOH’s PEWIDTH bits that are strapping options for configuring the PCI Express* ports at
system power-on.
Each of the Intel
®
Server System SR2600/SR2625/SR1600/SR1625 risers
has been optimally defined to strap the PEWIDTH bits through the Riser Type pins to either
eliminate or reduce the need for software configurations of the PCI Express* ports.
IOH’s PEWIDTH contains a total of six bits. The acceptable values of PEWIDTH ranges from
PEWIDTH[5:0] = 00_0000b to PEWIDTH[5:0] = 11_1011b.
For a description of how PEWIDTH
configures the PCI Express* lanes, refer to the Intel
®
5500/5520 Chipset I/O Hub (IOH) External
Design Specification.
A subset of the supported values and resulting configuration is shown in
the following table.