Technical Product Specification
Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS
Intel order number E44031-012 Revision 1.9
106
6.7 Riser Card Slot
The server board has one riser slot, utilizing Intel
®
Adaptive Slot Technology, which serves both
full-height and half-height cards with PCI-X and/or PCI-Express* interface depending on
chassis configuration.
Note: The PCI-X interface is supported using 2U Butterfly PCI Express*/PCI-X active riser.
The riser connector is a 280-pin PCI Express* connector from FCI-Berg (Vendor P/N:
10027747-11110TLF).
The pin-out defines four Power Rails (3.3V, 3.3VAUX, 5V, 12V, and
N12V), 24 lanes of PCI Express* Gen2 lanes, seven Reference Clocks along with various
sideband signals. One RSVD pin is strapped to the ground on the server board and is not used
on the Riser.
The pin-out defines the PCI Express* signals in two ways:
TP[x] and TN[x] are the generic signal names indicating the Transmit pairs; RP[x] and
RN[x] are the generic signal names indicating the Receive pairs.
PEx_Tx[x] and PEx_Rx[x] are the actual signal names used in the design.
Table 62. Pin-out of adaptive riser slot
Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
1
3.3V
3.3V
1
70
GND
RP[6] { PE5_Rp [1] }
70
2 3.3V 3.3V 2 71 GND RN[6] { PE5_Rn [1] } 71
3
GND
3.3V
3
72
TP[5] { PE5_Tp [2] }
GND
72
4
GND
3.3V
4
73
TN[5] { PE5_Tn [2] }
GND
73
5 GND 3.3V 5 74 GND RP[5] { PE5_Rn [2] } 74
6
GND
3.3V
6
75
GND
RN[5] { PE5_Rp [2] }
75
7
GND
3.3V
7
76
TP[4] { PE5_Tp [3] }
GND
76
8 GND 3.3V 8 77 TN[4] { PE5_Tn [3] } GND 77
9
GND
3.3V
9
78
GND
RP[4] { PE5_Rp [3] }
78
10
3.3V
3.3V
10
79
GND
RN[4] { PE5_Rn [3] }
79
11 3.3V 3.3V 11 80 TP[3] { PE6_Tp [0] } GND 80
KEY
KEY
KEY
KEY
81
TN[3] { PE6_Tn [0] }
GND
81
KEY
KEY
KEY
KEY
82
GND
RP[3] { PE6_Rn [0] }
82
12
GND
3.3V
12
83
GND
RN[3] { PE6_Rp [0] }
83
13
GND
3.3V
13
84
TP[2] { PE6_Tp [1] }
GND
84
14
3.3VAUX
3.3V
14
85
TN[2] { PE6_Tn [1] }
GND
85
15
3.3VAUX
3.3V
15
86
GND
RP[2] { PE6_Rp [1] }
86
16
GND
12V
16
87
GND
RN[2] { PE6_Rn [1] }
87
17
GND
12V
17
88
TP[1] { PE6_Tn [2] }
GND
88
18
GND
12V
18
89
TN[1] { PE6_Tp [2] }
GND
89
19 GND 12V 19 90 GND RP[1] { PE6_Rn [2] } 90
20
GND
12V
20
91
GND
RN[1] { PE6_Rp [2] }
91
21
GND
12V
21
92
TP[0] { PE6_Tp [3] }
GND
92