Service Guide

156 Intel
®
Server System SR2600UR/SR2625UR Service Guide
Chipset
0x21h X X O X X X X O Initializing a chipset component
Memory
0x22h X X O X X X O X Reading configuration data from
memory (SPD on DIMM)
0x23h X X O X X X O O Detecting presence of memory
0x24h X X O X X O X X Programming timing parameters in the
memory controller
0x25h X X O X X O X O Configuring memory parameters in the
memory controller
0x26h X X O X X O O X Optimizing memory controller settings
0x27h X X O X X O O O Initializing memory, such as ECC init
0x28h X X O X O X X X Testing memory
PCI Bus
0x50h X O X O X X X X Enumerating PCI buses
0x51h X O X O X X X O Allocating resources to PCI buses
0x52h X O X O X X O X Hot Plug PCI controller initialization
0x53h X O X O X X O O Reserved for PCI bus
0x54h X O X O X O X X Reserved for PCI bus
0x55h X O X O X O X O Reserved for PCI bus
0x56h X O X O X O O X Reserved for PCI bus
0x57h X O X O X O O O Reserved for PCI bus
USB
0x58h X O X O O X X X Resetting USB bus
0x59h X O X O O X X O Reserved for USB devices
Table 9. Diagnostic LED POST Code Decoder
Checkpoint
Diagnostic LED Decoder
Description
O=On; X=Off
Upper Nibble Lower Nibble
MSB LSB
8h 4h 2h 1h 8h 4h 2h 1h
LED #7 #6#5#4#3#2#1#0