Technical Product Specification

Intel® Workstation System SC5650SCWS TPS Functional Architecture

Revision 1.2

Intel order number: E81822-002

3.14 IEEE 1394a Support

The Intel

Workstation System SC5650SCWS provides two IEEE 1394a ports via a Texas

Instruments* TSB43AB22A: an external 6-pin IEEE 1394a port through rear I/O panel and an

internal 2x5 pin IEEE 1394a port.

Both of the 1394 ports are capable of transferring data between the 32-bit/33-MHz PCI bus and

the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s.

Note: Boot from IEEE 1394a device is not supported by the Intel

Workstation System

SC5650SCWS.

The feature list for the Texas Instruments* TSB43AB22A is as follows:

 Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus

and IEEE Std 1394a-2000.

 Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394.

 Compliant with Intel Mobile Power Guideline 2000.

 Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,

multi-speed concatenation, arbitration acceleration, fly-by concatenation, and port

disable/suspend/resume.

 Power-down features to conserve energy in battery-powered applications include:

automatic device power down during suspend, PCI power management for link-layer,

and inactive ports powered down.

 Ultralow-power sleep mode

 Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and

400M bits/s.

 Cable ports monitor line conditions for active connection to remote node.

 Cable power presence monitoring.

 Separate cable bias (TPBIAS) for each port.

 1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI

signaling environments.

 Physical write posting of up to three outstanding transactions.

 PCI burst transfers and deep FIFOs to tolerate large host latency.

 PCI_CLKRUN protocol

 External cycle timer control for customized synchronization.

 Extended resume signaling for compatibility with legacy DV components.

 PHY-Link logic performs system initialization and arbitration functions.

 PHY-Link encode and decode functions included for data-strobe bit level encoding.

 PHY-Link incoming data resynchronized to local clock.

 Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s,

200M bits/s, and 400M bits/s.

 Node power class information signaling for system power management.

 Serial ROM interface supports 2-wire serial EEPROM devices.