Datasheet

Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder
Revision 1.9
Intel order number E53971-008
91
Table 57. Diagnostic LED POST Code Decoder
Checkpoint
Diagnostic LED Decoder
Description
1 = On, 0=Off
Upper Nibble
Lower Nibble
MSB
LSB
8h
4h
2h
1h
8h
4h
2h
1h
LED
#7
#6
#5
#4
#3
#2
#1
#0
Host Processor
0x10h
0
0
0
1
0
0
0
0
Power-on initialization of the host processor (bootstrap processor)
0x11h
0
0
0
1
0
0
0
1
Host processor cache initialization (including AP)
0x12h
0
0
0
1
0
0
1
0
Starting application processor initialization
0x13h
0
0
0
1
0
0
1
1
SMM initialization
0x14h
0
0
0
1
0
1
0
0
Selection of Processor with least features to be used as Boot Strap
Processor
0x15h
0
0
0
1
0
1
0
1
Switch an AP processor to become the new Boot Strap Processor
Chipset
0x21h
0
0
1
0
0
0
0
1
Initializing a chipset component
Memory
0x22h
0
0
1
0
0
0
1
0
Reading configuration data from memory (SPD on FBDIMM)
0x23h
0
0
1
0
0
0
1
1
Detecting presence of memory
0x24h
0
0
1
0
0
1
0
0
Programming timing parameters in the memory controller
0x25h
0
0
1
0
0
1
0
1
Configuring memory parameters in the memory controller
0x26h
0
0
1
0
0
1
1
0
Optimizing memory controller settings
0x27h
0
0
1
0
0
1
1
1
Initializing memory, such as ECC init
0x28h
0
0
1
0
1
0
0
0
Testing memory
0xE4h
1
1
1
0
0
1
0
0
BIOS cannot communicate with DIMM (serial channel hardware
failure)
0xE6h
1
1
1
0
0
1
1
0
DIMM(s) failed Memory iBIST or Memory Link Training failure
0xE8h
1
1
1
0
1
0
0
0
No memory available (system halted)
0xE9h
1
1
1
0
1
0
0
1
Unsupported or invalid DIMM configuration (system halted)
0xEAh
1
1
1
0
1
0
1
0
DIMM training sequence failed (system halted)
0xEBh
1
1
1
0
1
0
1
1
Memory test failed (system halted)
0xECh
1
1
1
0
1
1
0
0
Unsupported or invalid DIMM configuration (system halted)
0xEDh
1
1
1
0
1
1
0
1
Unsupported or invalid DIMM configuration (system halted)
0xEBh
1
1
1
0
1
0
1
1
DIMM with corrupted SPD data detected (system halted)