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Server Board S5500WB

Technical Product Specification

Intel order number E53971-008

Revision 1.9

February, 2012

Enterprise Platforms and Services Division

Summary of content (117 pages)

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Intel® Server Board S5500WB Technical Product Specification Intel order number E53971-008 Revision 1.
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Revision History Intel® Server Board S5500WB TPS Revision History Date 03/30/2009 Revision Number 1.0 Modifications Initial Release. 04/29/2009 1.1 Formatting corrections. 05/20/2009 1.2 Updated heatsink installation steps. Corrected processor fault table. Added jumper location figure. 08/03/2009 1.3 Updated memory support. Corrected PCIe slot speed. Removed S4 support. 01/12/2010 1.4 Corrected USB header pin-out. 03/09/2010 1.5 Updated Power Supply communication bus requirements.
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Intel® Server Board S5500WB TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Board S5500WB TPS Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Section Outline ....................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 1 2. Server Board Overview ................................
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Intel® Server Board S5500WB TPS 3.7.2 3.8 Table of Contents USB 2.0 Support .................................................................................................. 29 Network Interface Controller (NIC) ....................................................................... 30 3.8.1 MAC Address Definition ....................................................................................... 31 3.8.2 LAN Connector Ordering ....................................................................
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Table of Contents Intel® Server Board S5500WB TPS 5.5.2 PCI Express* Power management ....................................................................... 43 5.5.3 PMBus* ................................................................................................................ 43 5.6 5.6.1 I2C\SMBUS Architecture Block ............................................................................ 44 I2C\SMBUS Device Addresse ......................................................................
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Intel® Server Board S5500WB TPS Table of Contents 7.4.6 Serial Port Connectors ......................................................................................... 66 7.4.7 USB Connectors .................................................................................................. 66 7.5 Fan Headers ........................................................................................................ 67 8. Intel® Light-Guided Diagnostics ..................................................
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Table of Contents Intel® Server Board S5500WB TPS 11.3.1 FCC Verification Statement (USA) ....................................................................... 86 11.3.2 ICES-003 (Canada) .............................................................................................. 87 11.3.3 Europe (CE Declaration of Conformity) ................................................................ 88 11.3.4 BSMI (Taiwan) .................................................................................
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Intel® Server Board S5500WB TPS List of Figures List of Figures Figure 1. Intel® Server Board S5500WB 12V .............................................................................. 4 Figure 2. Intel Server Board S5500WB SSI ................................................................................ 5 Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown) ........................... 6 Figure 4. Rear Panel Connector Placement: ........................................................
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List of Figures Intel® Server Board S5500WB TPS Figure 32. Power Distribution Diagram ..................................................................................... 83 Figure 33. Diagnostic LED Placement Diagram ........................................................................ 89 x Revision 1.
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Intel® Server Board S5500WB TPS List of Tables List of Tables Table 1. Intel® Server Board S5500WB Feature Set ................................................................... 2 Table 2. Intel® Server Board S5500WB System Interconnects ................................................... 7 Table 3. Intel® Server Board S5500WB Features ..................................................................... 13 Table 4. Mixed Processor Configurations...........................................................
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List of Tables Intel® Server Board S5500WB TPS Table 32. SGPIO Header (J1B1) .............................................................................................. 55 Table 33. Front Panel SSI Standard 24-pin Connector Pin-out (J1E2) ...................................... 55 Table 34. Power LED Indicator States ...................................................................................... 57 Table 35. System Status LED .......................................................................
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Intel® Server Board S5500WB TPS List of Tables Revision 1.
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Intel® Server Board S5500WB TPS 1. Introduction Introduction The Intel® Server Board S5500WB is a dual socket server using the Intel® Xeon® Processor 5500 series and 5600 series processors, in combination with the IOH and ICH10R to provide a balanced feature set between technology leadership and cost. 1.1 Section Outline This document is divided into the following chapters: 1.
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Server Board Overview 2. Intel® Server Board S5500WB TPS Server Board Overview The Intel® Server Board S5500WB is a monolithic printed circuit board (PCB) with features designed to support the Internet Portal Data Center markets. The following table provides a high-level product feature list. ® Table 1.
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Intel® Server Board S5500WB TPS Server Board Overview Feature System Fan Support Description Two 8-pin fan headers for double rotor memory fans and six 4-pin fan headers supporting two processor zones and two memory zones in a redundant fashion Add-in Adapter Support One riser slot supporting both full-height and low-profile 1U and 2U MD2 PCI Express* x16 riser cards PCI gen2 Express* x8 w/ x16 connector. One riser slot supporting PCI Express* x8 riser cards PCI gen2 Express* x4 w/ x8 connector.
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Server Board Overview 2.1 Intel® Server Board S5500WB TPS Intel® Server Board S5500WB Server Board The Intel® Server Board S5500WB has two board SKUs, such as SSI-compliant and 12-V-onlySKU. The board layouts of the SKUs are shown. ® Figure 1. Intel Server Board S5500WB 12V 4 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 2. Intel Server Board S5500WB SSI Revision 1.
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Server Board Overview 2.2 Intel® Server Board S5500WB TPS Server Board Connector and Component Layout ® Figure 3. Intel Server Board S5500WB Components (both SKUs are shown) 6 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview ® Table 2.
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Server Board Overview 2.2.1 Intel® Server Board S5500WB TPS Board Rear Connector Placement ® The Intel Server Board S5500WB has the following board rear connector placement: Figure 4. Rear Panel Connector Placement: A ID LED Description E Description RJ-45 GbE LAN connector B Status LED F RJ-45 Serial port connector C RJ-45 GbE/Dual USB connector G DB15 Video D Dual USB connector H Diagnostic LEDs 2.2.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 5. Baseboard and Mounting holes Revision 1.
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Server Board Overview Intel® Server Board S5500WB TPS Figure 6. Connector Locations 10 Revision 1.
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Intel® Server Board S5500WB TPS Server Board Overview Figure 7. Primary Side Height Restrictions Revision 1.
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Server Board Overview Intel® Server Board S5500WB TPS Figure 8. Secondary Side Height Restrictions 12 Revision 1.
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Intel® Server Board S5500WB TPS 3. Functional Architecture Functional Architecture The Intel® Server Board S5500WB is a purpose build, power-optimized server used in a 1U rack. Memory and processor socket placement is made to minimize the amount of fan power required to cool these components. Voltage Regulators (VRDs) are optimized for a particular range of memory and CPU power that suits the target Internet Portal Datacenter (IPDC) segment of the market.
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Functional Architecture 3.2 Intel® Server Board S5500WB TPS Functional Block Diagram ® Figure 9. Intel Server Board S5500WB Functional Block Diagram 14 Revision 1.
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Intel® Server Board S5500WB TPS 3.3 Functional Architecture Processor Subsystem The Intel® 5500 series and the next generation Intel® 5600 series processors support the following key technologies:  Intel® Integrated Memory Controller  Point-to-point link interface based on the Intel® QuickPath Interconnect (Intel® QPI), which was formerly known as the Common System Interface (CSI). The Intel® 5500 series processor is a multi-core processor based on the 45 nm process technology.
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Functional Architecture Intel® Server Board S5500WB TPS Table 4. Mixed Processor Configurations Error Processor family not identical Severity Fatal System Action The BIOS detects the error condition and responds as follows:  Logs the error into the system event log (SEL).  Alerts the Integrated BMC of the configuration error with an IPMI command.  Does not disable the processor.  Displays ―0194: Processor family mismatch detected‖ message in the error manager.  Halts the system.
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Intel® Server Board S5500WB TPS 3.3.3 Functional Architecture Installing or Replacing the Processor 3.3.3.1 Installing the Processor To install a processor, follow these instructions: 1. 2. 3. 4. Turn off all peripheral devices connected to the server. Turn off the server. Disconnect the AC power cord from the server. Remove the server’s cover. See the document that came with your server chassis for instructions on removing the server’s cover. 5.
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Functional Architecture Intel® Server Board S5500WB TPS Figure 12. Installing processor 9. Lower the load plate and load lever of the ILM cover completely. Note: Make sure the alignment triangle mark and the alignment triangle cutout align correctly. To assist in package orientation and alignment with the socket: A. The package Pin1 triangle and the socket Pin1 chamfer provide a visual reference for proper orientation. B.
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Intel® Server Board S5500WB TPS Functional Architecture Figure 13. Package Installation/Remove Feature 3.3.3.2 Installing the Processor Heatsink(s) CAUTION: The heatsink has Thermal Interface Material (TIM) located on the bottom of it. Use caution when you unpack the heatsink so you do not damage the TIM To install the heatsink, follow these steps: 1. Remove the protective film on the TIM if present. 2. Orient the heatsink over the processor as shown in Figure 14.
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Functional Architecture Intel® Server Board S5500WB TPS Figure 14. Installing/Removing Heatsink 3.3.3.3 Removing the Processor Heatsink To remove the heatsink, follow these steps: 1. Loosen the four captive screws on the heatsink corners in a diagonal manner according to the numbers shown in Figure 1 as follows: a) Starting with the screw at location 1, loosen it by giving it two rotations in the anticlockwise direction and stop. (IMPORTANT: Do not fully loosen.
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Intel® Server Board S5500WB TPS Functional Architecture In the current implementation, Intel® QPI ports are capable of operating at transfer rates of up to 6.4 GT/s. Intel® QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and quarter - 5 lanes) independently in each direction between a pair of devices communicating via the Intel® QPI. The server boards support full-width communication only. For more information see the Intel® QPI Overview Rev 1.04 (Document#: 380531) 3.
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Functional Architecture Intel® Server Board S5500WB TPS The memory channels from socket 1 are identified as Channels A, B, and C. The memory channels from socket 2 are identified as Channels D, E, and F. The DIMM identifiers on the silkscreen on the board provide information about the channel, and, therefore the processor, to which they belong. For example, DIMM_A1 is the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2. Table 5.
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Intel® Server Board S5500WB TPS Functional Architecture The BIOS will always enable high-memory reclaim if it discovers installed physical memory equal to or greater than 4 GB. For the operating system, the reclaimed memory is recoverable only when it supports and enables the PAE feature in the processor. Most operating systems support this feature. For details, see the relevant operating system manuals. 3.4.
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Functional Architecture Intel® Server Board S5500WB TPS Figure 17. Installing Memory 4. Make sure the clips at either end of the DIMM socket(s) are pushed outward to the open position (see letter ―A‖ in the figure above). 5. Holding the DIMM by the edges, remove it from its anti-static package. 6. Position the DIMM above the socket. Align the two small notches in the bottom edge of the DIMM with the keys in the socket (letter ―B‖ in Figure 16). 7.
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Intel® Server Board S5500WB TPS 3.4.8 Functional Architecture Channel-Independent Mode In the Independent Channel mode, you can populate multiple channels in any order (for example, you can populate channels B and C while channel A is empty). Also, DIMMs on adjacent channels do not need to have identical parameters. Therefore, all DIMMs are enabled and used in the Independent Channel mode. Adjacent slots on channels A and D do not need matching size and organization.
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Functional Architecture Intel® Server Board S5500WB TPS Figure 18. Mirroring Memory Configuration 3.4.10 Memory Error LED Each DIMM is allocated an LED that, when lit, indicates a memory DIMM failure. It is the function of the BIOS to identify bad DIMMs during the boot process. The BIOS sends a message to the BMC to indicate which DIMM LED needs turn on. 3.5 Intel® 5500 Chipset IOH The Intel® 5500 Chipset component is an I/O Hub (IOH).
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Intel® Server Board S5500WB TPS Functional Architecture Table 6. IOH24D PCI Express* Bus Segments PCI Bus Segment Port 0 ICH10R Width x4 Speed 10 Gb/s Type PCI Express* Gen1 PCI I/O Card Slots x4 PCI Express* Gen1 throughput to the ICH10R southbridge PE1, PE2 ® Intel 5500 Chipset IOH PCI Express* x4 10 Gb/s PCI Express* Gen1 x4 PCI Express* Gen1 throughput to an onboard NIC. PE3, ® Intel 5500 Chipset IOH PCI Express* X4 20 Gb/S PCI Express* Gen2 X4 PCI Express* Gen2 throughput to slot 1.
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Functional Architecture Intel® Server Board S5500WB TPS The functionality provided by the SPS firmware is different from Intel® Active Management Technology (Intel® AMT or AT) provided by the ME on client platforms. Server Platform Services are value-added platform management options that enhance the value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O components).
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Intel® Server Board S5500WB TPS Functional Architecture server board are numbered SATA-1 through SATA-6. You can enable or disable the SATA ports and/or configure them by accessing the BIOS setup utility during POST. 3.7.1.
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Functional Architecture 3.8 Intel® Server Board S5500WB TPS Network Interface Controller (NIC) Network interface support is provided from the onboard Intel® 82576 NIC, which is a single, compact component with two fully integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports. The Intel® 82576 NIC provides the server board with support for dual LAN ports designed for 10/100/1000 Mbps operation.
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Intel® Server Board S5500WB TPS 3.8.1 Functional Architecture MAC Address Definition ® The Intel Server Board S5500WB has the following four MAC addresses assigned to it at the Intel factory.
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Functional Architecture Intel® Server Board S5500WB TPS  Two 16C550 compatible serial ports  Serial IRQ support  16 GPIO ports (shared with Integrated BMC)  LPC to SPI Bridge for system BIOS support  SMI and PME support  ACPI compliant  Wake-up control The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features:  USB 2.
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Intel® Server Board S5500WB TPS Functional Architecture Figure 19. Integrated BMC Hardware 3.9.1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These interfaces are not shared with the host system. At any time, you can enable only one dedicated interface for management traffic. The default active interface is the NIC 1 port. For these channels, you can enable support for IPMI-over-LAN and DHCP.
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Functional Architecture 3.9.2 Intel® Server Board S5500WB TPS RMM3 Advanced Management Board: The RMM3 advanced management board serves two purposes. The first is to give the customer the option to add a dedicated management 100-Mbit LAN interface to the product. The second is to give additional flash space, enabling the Advanced Management functions to support WS-MAN and CIMOM. The RMM3 comes with a third 10/100GbE NIC that connects to the board. RMM3 management traffic can use the third NIC or NIC 1.
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Intel® Server Board S5500WB TPS 3.12.1 Functional Architecture Video Modes The integrated video controller supports all standard VGA modes. The following table shows the 2D modes supported for both CRT and LCD. Table 9. Supported Video Modes 3.12.2 Dual Video The BIOS supports both single-video and dual-video modes. The dual-video mode is enabled by default in the BIOS. In the single mode (dual monitor video = disabled), the onboard video controller is disabled when an add-in video card is detected.
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Functional Architecture Intel® Server Board S5500WB TPS ® The Intel Server Board S5500WB provides a mechanism to support video to the front panel via the use of an internal header. When a monitor is plugged into the front panel video connector, the rear panel video stream is disconnected. There is a jumper option to change this default action.
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Intel® Server Board S5500WB TPS 3.13.4 Functional Architecture I/O Module Connector Mezanine connectors are provided to support the various I/O modules, both the older Gen 1 I/O modules supported by Intel® Server Board S5000PAL and newer, double-wide Gen 2 I/O modules supported by the Intel® Server Board S5520UR are supported on the Intel® Server Board S5500WB.
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Intel® I/O Expansion Modules 4. Intel® Server Board S5500WB TPS Intel® I/O Expansion Modules The Intel® Server Board S5500WB supports a variety of I/O Module options using 2x4 PCI ® Express* Gen2 Intel I/O Expansion Module connectors on the rear of the server board. Each ® Intel I/O Expansion Module connector is a 50-pin, surface mount, 0.8mm pitch, header.
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Intel® Server Board S5500WB TPS Product Code Functional Architecture Description AXX4GBIOMOD2 Quad port Gigabit Ethernet I/O Expansion Module based on ® the Intel 82576EB Gigabit Ethernet Controller. AXXIBQDRMOD InfiniBand* I/O Expansion Module Single Port QDR. For more information, refer to the I/O modules in the Intel® I/O Expansion Modules Hardware Specification. Revision 1.
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Platform Management Features 5. Intel® Server Board S5500WB TPS Platform Management Features This section explains BIOS and firmware (FW) requirements that drive specific hardware implementations of the platform. To a large extent, this is background information. 5.1 BIOS Feature Overview The Intel® Server Board S5500WB product uses the AMI Aptio v3.x code base. 5.1.1 EFI Support The platform BIOS is compiled to support the 64-bit EFI environment, natively.
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Intel® Server Board S5500WB TPS Platform Management Features The Server Engines Pilot II baseboard management controller across Intel’s server product line with two different management feature set configurations: Basic and Advanced. The Intel® Server Board S5500WB supports both. Basic features include IPMI 2.0 support, remote management, hardware monitoring, event management, event alerting, system event log, asset inventory, console redirection, web interface, and SMASH CLP (basic feature set).
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Platform Management Features Intel® Server Board S5500WB TPS Feature SMASH CLP (Basic) Description Command line SSH interface for basic server management operations Node Manager Power management by using P-state\C-State cycling method Requires PMBus* power supply. 5.2.4 BMC Advanced Features ® The Intel Server Board S5500WB product includes support for an upgrade module to support the advanced server management functionality.
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Intel® Server Board S5500WB TPS Platform Management Features grouped together with one or more features in flexible combinations to allow OEMs to differentiate platforms. 5.3.2 BMC - Management Engine Interaction Management Engine-Integrated BMC interactions include the following:  Integrated BMC stores sensor data records for ME-owned sensors.  Integrated BMC participates in ME firmware update.  Integrated BMC initializes ME-owned sensors based on SDRs.
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Platform Management Features 5.6 Intel® Server Board S5500WB TPS I2C\SMBUS Architecture Block Figure 20. S5500WB I2C\SMBUS Block Diagram 5.6.1 I2C\SMBUS Device Addresses Table 21 lists the I2C\SMBus addresses of various devices by bus. Table 16.
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Intel® Server Board S5500WB TPS Platform Management Features Main Bus LAN Power Rail 3V3SB Sub Bus NA Power Rail NA Link 3V3SB NA NA PWR 5V NA DDC NA 5V Spare DDC 3V3SB 3V3SB Device I2C\SMBus Address Note IBMC I2C\SMBus 5 NIC LAN IBMC I2C\SMBus 4 ICH10R SMLINK PS FRU PS I2C\PSMI IBMC I2C\SMBus 2 IBMC GFX DDC 0x88 0xAC 0xB0 Video Monitor 0xA0 Revision 1.
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Configuration Jumpers 6. Intel® Server Board S5500WB TPS Configuration Jumpers The following table provides a summary and description of configuration, test, and debug ® jumpers on the Intel Server Board S5500WB. The server board has several 3-pin jumper blocks that can be used. Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼ Figure 21: Jumper Blocks (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2, J7A2) 46 Revision 1.
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Intel® Server Board S5500WB TPS Configuration Jumpers Table 17: Server Board Jumpers (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2) J1B5: BMC Force Update jumper 1-2 Mode of Operation Normal 2-3 Update IBMC GPIO[1] is pulled LOW. J1C2: Password Clear 1-2 Normal ICH10R INTRUDER# pin is pulled HIGH. Default position. 2-3 Clear Password ICH10R INTRUDER# pin is pulled LOW. 1-2 Normal ICH10R GPIO [55] is pulled HIGH. Default position. 2-3 Recovery ICH10R GPIO [55] is pulled LOW.
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Configuration Jumpers Intel® Server Board S5500WB TPS 6. Perform the BMC firmware update procedure as documented in the README.TXT file included in the given BMC firmware update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating the BMC is still in update mode. 7. Power down and remove the AC power cord. 8. Open the server chassis. 9.
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Intel® Server Board S5500WB TPS 6.1.3 Configuration Jumpers BIOS Recovery Mode (J1C3) The Intel® Server Board S5500WB uses BIOS recovery to repair the system BIOS from flash corruption in the main BIOS and Boot Block. This 3-pin jumper is used to reload the BIOS when the image is suspected to be corrupted. For directions on how to recover the BIOS, refer to the specific BIOS release notes. Table 20.
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Configuration Jumpers 6.1.4 Intel® Server Board S5500WB TPS Reset BIOS Configuration (J1B4) This jumper used to be the CMOS Clear jumper. Since the previous generation, the BIOS has moved CMOS data to the NVRAM region of the BIOS flash. The BIOS checks during boot to determine if the data in the NVRAM needs to be set to default. Table 21. Reset BIOS Jumper Jumper Position 1-2 2-3 Mode of Operation Normal Reset BIOS Configuration Note ICH10R RTCRST# pin is pulled HIGH. Default position.
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Intel® Server Board S5500WB TPS 6.1.6 Configuration Jumpers ME Firmware Force Update (J7A2) 1-2 Pins ME Firmware Update Mode Disabled (Default) 2-3 Enabled The ME firmware consists of two operational images and a recovery image. During boot, the recovery loader is started first and it tries to load the active firmware image by running the loader of this image. If it fails to boot, it tries to boot the other operational image. If both fail, the recovery loader starts in recovery mode.
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Connector/Header Locations and Pin-out Intel® Server Board S5500WB TPS 7. Connector/Header Locations and Pin-out 7.1 Power Connectors Table 23. SSI SKU 24-pin 2x12 Connector (J9B3) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name +3.3V +3.3V GND +5V GND +5V GND PWR_GD SB5V +12V +12V +3.3V Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name +3.3V -12V GND PS_ON GND GND GND NC +5V +5V +5V GND Table 24.
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Intel® Server Board S5500WB TPS Connector/Header Locations and Pin-out Table 26. 12-V only 2x4 Connector (replaces EPSD12V 2x12 connector) (J9D2) Pin 1 2 3 4 5 6 7 8 Signal Name GND GND GND GND +12V +12V +12V +12V Table 27. 12-V Only Power Control (replaces the 1x5 power control) (J9D1) (FOXCONN ELECTRONICS INC HF1107V-P1 or TYCO ELECTRONICS CORPORATION 5-104809-6) Pin Signal Name 1 2 3 4 SMB_PWR_CLK SMB_PWR_DAT SMB_PWR_ALRT Remote Sense Return 5 6 7 12V Remote Sense PS_ON 5V S/B Table 28.
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Connector/Header Locations and Pin-out 7.2 7.2.1 Intel® Server Board S5500WB TPS System Management Headers Intel® Remote Management Module 3 (Intel ® RMM3) Connector A 34-pin Intel® RMM 3 connector (J5B1) is included on the server board to support the optional Intel® Remote Management Module 3. There is no support for third-party management cards on this server board.
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Intel® Server Board S5500WB TPS 7.2.3 Connector/Header Locations and Pin-out Hard Drive Activity (Input) LED Header Table 47. SATA HDD Activity (Input) LED Header (J1D2) Pin 1 2 7.2.4 Description LED_HD_ACTIVE_L NC IPMB Header Table 31. IPMB Header 4-pin (J1B2) Pin 1 2 3 4 7.2.5 Signal Name SMB_IPMB_5VSB_DAT GND SMB_IPMB_5VSB_CLK P5V_STBY Description BMC IPMB 5V standby data line Ground BMC IPMB 5V standby clock line +5V standby power SGPIO Header Table 32. SGPIO Header (J1B1) Pin 1 2 3 4 7.
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Connector/Header Locations and Pin-out Intel® Server Board S5500WB TPS Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs. The following sections describe the supported functionality of each control panel feature. 7.3.1 Power Button The BIOS supports a front control panel power button. Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset.
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Intel® Server Board S5500WB TPS 7.3.5 Connector/Header Locations and Pin-out Power LED The green power LED is active when the system DC power is on. The power LED is controlled by the BIOS. The power LED reflects a combination of the state of system (DC) power and the system ACPI state. The following table identifies the different states that the power LED can assume. Table 34. Power LED Indicator States State Power off Power on S5 S1 Sleep S0 7.3.
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Connector/Header Locations and Pin-out Intel® Server Board S5500WB TPS Table 35. System Status LED Color Green State Solid on Ok System Status System ready Description Green ~1 Hz blink Degraded BIOS detected 1. Unable to use all of the installed memory (more than one DIMM installed).1 2. In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2). 1 3. PCI Express* correctable link errors. Integrated BMC detected 1.
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Intel® Server Board S5500WB TPS 7.3.7 Connector/Header Locations and Pin-out Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced. The state of the chassis ID LED is affected by the following:  Toggled by the chassis ID button  Controlled by the Chassis Identify command (IPMI)  Controlled by the Chassis Identify LED command (OEM) Table 36.
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Connector/Header Locations and Pin-out Intel® Server Board S5500WB TPS Pin Side B 13 PCI Express* Signal GND PCI Express* Signal REFCLK+ Pin Side A 13 14 PETxP0 REFCLK- 15 PETxN0 16 Pin Side B Pin Side A 55 PCI Express* Signal PETxN9 PCI Express* Signal GND 14 56 GND PERxP9 56 GND 15 57 GND PERxN9 57 GND PERxP0 16 58 PETxP10 GND 58 17 PRSNT2# PERxN0 17 59 PETxN10 GND 59 18 GND GND 18 60 GND PERxP10 60 19 PETxP1 RSVD 19 61 GND PERxN10 61 20 PETxN1
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Intel® Server Board S5500WB TPS Pin-Side B 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 7.4.
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Connector/Header Locations and Pin-out Pin Intel® Server Board S5500WB TPS Signal Name Description 8 GND Ground 9 TP_VID_CONN_B9 No connection 10 GND Ground 11 TP_VID_CONN_B11 No connection 12 V_IO_DDCDAT DDCDAT 13 V_IO_HSYNC_CONN HSYNC (horizontal sync) 14 V_IO_VSYNC_CONN VSYNC (vertical sync) 15 V_IO_DDCCLK DDCCLK The following table details the pin-out definition of the internal VGA connector (J1D1): Table 40. VGA Internal Video Connector (J1D1) 7.4.
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Intel® Server Board S5500WB TPS Connector/Header Locations and Pin-out Table 41. RJ-45 10/100/1000 NIC Connector Pin-out (J8A2, J9A1) Revision 1.
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Connector/Header Locations and Pin-out 7.4.4 Intel® Server Board S5500WB TPS SATA Connectors The server board provides up to six SATA / SAS connectors:  SATA-0 (J9B2)  SATA-1 (J9B3)  SATA-2 (J9C1)  SATA-3 (J9C2)  SATA-4 (J9B5)  SATA-5 (J9B4) The pin configuration for each connector is identical and defined in the following table. Table 42. SATA Connectors Pin 1 2 3 4 5 6 7 7.4.
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Intel® Server Board S5500WB TPS Connector/Header Locations and Pin-out ® Table 43. 50-pin Intel I/O Expansion Module Connector Pin-out (J2B1, J3B1) Revision 1.
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Connector/Header Locations and Pin-out 7.4.6 Intel® Server Board S5500WB TPS Serial Port Connectors The server board provides one external RJ-45 Serial A port (J7A1) and one internal 9-pin serial B header (J1A2). The following tables define the pin-outs. Table 44. External RJ-45 Serial Port A (COM1) (J7A1) Pin 1 2 3 4 Signal Name SPA_RTS SPA_DTR SPA_SOUT_N GND Pin 5 6 7 8 Signal SPA_RI SPA_SIN SPA_DSR SPA_CTS Table 45. Internal 9-pin Serial B (COM2) (J1A2) Pin 1 3 5 7 9 7.4.
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Intel® Server Board S5500WB TPS Connector/Header Locations and Pin-out Table 48. Low-Profile Internal USB Connector (J1E3) Pin 1 3 5 7 9 7.5 Signal Name +5V USB_N USB_P GND Key Pin Pin 2 4 6 8 10 Signal Name NC NC NC NC LED# Fan Headers The server board provides six SSI-compliant 4-pin fan headers and two 8-pin fan headers to be used for CPU, and IO cooling. The pin configuration for each of the 4-pin fan headers is identical and defined in the following tables. Table 49.
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Intel® Light-Guided Diagnostics 8. Intel® Server Board S5500WB TPS Intel® Light-Guided Diagnostics The server boards have several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description the location and function of each LED on the server board. 8.1 5-V Standby LED Several server management features of this server board require a 5-V stand-by voltage is supplied from the power supply.
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Intel® Server Board S5500WB TPS 8.2 Intel® Light-Guided Diagnostics Fan Fault LEDs Fan fault LEDs are present for the six fans and are located near each CPU fan header. A FLTMEM2R E FLTCPU1 B FLTMEM2 F FLTCPU1A C FLTCPU2A G FLTMEM1 D FLTCPU2 H FLTMEM1R Figure 23. Fan Fault LED Locations 8.3 System Status LED The server board provides LED for system status. The following figure shows the LED location. Revision 1.
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Intel® Light-Guided Diagnostics Intel® Server Board S5500WB TPS Figure 24. System Status LED Location The bi-color System Status LED operates as follows: 70 Revision 1.
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Intel® Server Board S5500WB TPS Intel® Light-Guided Diagnostics Table 51. System Status LED Color Green State Solid on System Status Ok Description System ready System degraded: BIOS detected 1. Unable to use all of the installed memory (more than one DIMM installed).1 2. In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2). 1 3. Green ~1 Hz blink Degraded PCI Express* correctable link errors. Integrated BMC detected 1.
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Intel® Light-Guided Diagnostics Color State Intel® Server Board S5500WB TPS System Status Description Fatal alarm – system has failed or shut down: BIOS Detected 1. DIMM failure when there is one DIMM present and no good memory is present.1 2. Run-time memory uncorrectable error in non-redundant mode.1 3. CPU configuration error (for instance, processor stepping mismatch). Amber Solid on Fatal Off N/A Not ready Integrated BMC Detected 1. CPU IERR signal asserted. 2. CPU 1 is missing. 3.
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Intel® Server Board S5500WB TPS 8.4 Intel® Light-Guided Diagnostics DIMM Fault LEDs Each DIMM slot has a DIMM Fault LED near the DIMM slot. Figure 25. DIMM Fault LEDs Locations A FLT_F E FLT_A2 B FLT_E F FLT_A1 C FLT_D1 G FLT_B D FLT_D2 H FLT_C Revision 1.
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Intel® Light-Guided Diagnostics 8.5 Intel® Server Board S5500WB TPS POST Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server board in the rear I/O area of the server board by the VGA connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® Server Board S5500WB TPS 8.6 Intel® Light-Guided Diagnostics Front Panel Support The Intel® Server Board S5500WB supports SSI standard front panel boards. The front panel support is provided by a SSI compatible 2x12-pin signal connector. The front panel connector supports the following diagnostic LEDs. Table 52.
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Design and Environmental Specifications Intel® Server Board S5500WB TPS 9. Design and Environmental Specifications 9.1 Fan Speed Control Thermal Management Fan speed control supports the following thermal sensors:  Discrete board level digital thermal sensor TMP75  Front panel Temp Sensor (if present)  CPU PECI DTS  DDR3 RDIMM TSOD Eight front system fan headers for four individual thermal zones  Zone 4 (mem2 fans) responds to memory2 and CPU2 temperatures.
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Intel® Server Board S5500WB TPS Design and Environmental Specifications The following tables show a basic location of the fan connectors on the board. The first line is the silk screen name of the connector; the second is the PWM signal name; the third is the Tach #; and the forth is the reference description. The last is the signal name associated with the fault LED signal. Figure 28: Location of Fan Connectors Table 53.
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Design and Environmental Specifications Intel® Server Board S5500WB TPS Table 54. Fan Connector Location & Detail CPU 2 Memory 2 FAN_CPU2 FAN_CPU2A FAN_MEM2 FAN_MEM2R PWM_CPU0 PWM_CPU0 PWM_MEM0 PWM_MEM0 Tach 3 Tach 7 Tach 4 Tach 4 & 8 J3E1 J2J2 J2J1 J1D5 LED_Fan_Fault_CPU0 LED_Fan_Fault_CPU0A LED_Fan_Fault_MEM0 LED_Fan_Fault_MEM0R Figure 29. Fans and Sensors Block Diagram 9.2 Thermal Sensors 9.2.
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Intel® Server Board S5500WB TPS    Design and Environmental Specifications Tcontrol offset Temperature = -2° C Pos_hyst = 0° C Neg_hyst = 3° C Those parameters in turn set the following:  Upper = - CPU PECI Tcontrol + Tcontrol offset  Lower = - CPU PECI Tcontrol + Tcontrol offset – 3C 9.2.2 Memory Temperature Sensor DDR3 cooling requires thermal throttling to protect memory from overheating. The Intel® Server Board S5500WB supports both DDR3 UDIMM and DDR3 RDIMM.
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Design and Environmental Specifications Intel® Server Board S5500WB TPS Figure 30: Temp Sensor Location A 9.3 Location U4K3 Description Temp Sensor - TMP75 Heatsinks The Intel® Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling. Chipset and or voltage regulator heatsinks are compatible with the 1U usage. 80 Revision 1.
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Intel® Server Board S5500WB TPS Design and Environmental Specifications Note: The Intel® Thermal Solution STS100P – Passive 1U/2U heatsink was tested for processors up to and including 95-W TDP (Thermal Design Power). Product order code: BXSTS100P 9.3.1 Unified Retention System Support The server board complies with the Intel® Unified Retention System (URS) and the Unified Backplate Assembly.
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Design and Environmental Specifications 9.4 Intel® Server Board S5500WB TPS Errors This section outlines how errors are routed in the hardware to ensure appropriate FW action (logging, fan control, system management, and so forth) is taken when an event occurs. 9.4.1 PROCHOT# PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the CPU.
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Intel® Server Board S5500WB TPS Power Subsystem 10. Power Subsystem 10.1 Server Board Power Distribution Figure 32. Power Distribution Diagram 10.2 Power Supply Compatibility The Intel® Server Board S5500WB is offered in two models:  SSI SKU: This version of the server board is designed to work with an ―off-the-shelf‖ multi-rail power supply that adheres to the SSI power specification: ―Power Supply Design Guideline for 2008 Dual-Socket Servers and Workstations‖.
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Power Subsystem Intel® Server Board S5500WB TPS The SSI uses the standard 24-pin and 8-pin power headers along with the 5pin Control connector. The 12-V only uses two 8-pin power headers, a 7-pin control header and a 6 pin HDD power connector. For maximum rack server efficiency, a DC 12-V only power supply is recommended. Appendix A shows connector pin outs. PMbus communications between the power supply and server board must comply with both SMBus and I2C Bus timing requirements. 10.
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Intel® Server Board S5500WB TPS Regulatory and Certification Information 11. Regulatory and Certification Information 11.1 Product Regulation Requirements Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations.
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Regulatory and Certification Information      Intel® Server Board S5500WB TPS BSMI Certification (Taiwan) GOST – Listed on one System Certification (Russia) Belarus – Listed on one System Certification (Belarus) KCC Certification (Korea) Ecology Declaration (International) 11.
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Intel® Server Board S5500WB TPS Regulatory and Certification Information For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
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Regulatory and Certification Information 11.3.3 Intel® Server Board S5500WB TPS Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance. 11.3.4 BSMI (Taiwan) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 11.3.
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Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Appendix A: POST Code LED Decoder During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board.
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Appendix A: POST Code LED Decoder Intel® Server Board S5500WB TPS In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Table 56.
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Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Table 57.
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Appendix A: POST Code LED Decoder QuickPath Interconnect (QPI) 0xA0h 1 0 1 0 0 0xA1h 1 0 1 0 0 0xA2h 1 0 1 0 0 0xA3h 1 0 1 0 0 0xA4h 1 0 1 0 0 0xA5h 1 0 1 0 0 0xA6h 1 0 1 0 0 0xA7h 1 0 1 0 0 0xA8h 1 0 1 0 1 0xA9h 1 0 1 0 1 0xAAh 1 0 1 0 1 0xABh 1 0 1 0 1 0xACh 1 0 1 0 1 0xADh 1 0 1 0 1 0xAEh 1 0 1 0 1 0xAFh 1 0 1 0 1 Integrated Memory Controller (IMC) 0xB0h 1 0 1 1 0 0xB1h 1 0 1 1 0 0xB2h 1 0 1 1 0 0xB3h 1 0 1 1 0 0xB4h 1 0 1 1 0 0xB5h 1 0 1 1 0 0xB6h 1 0 1 1 0 1 0 1 1 0 0xB7h 1 0 1 1 0xB8h 1 1 0 1 1 1 0xB
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Intel® Server Board S5500WB TPS USB 0x56h 0 1 0x57h 0 1 0x58h 0 1 0x59h 0 1 ATA/ATAPI/SATA 0x5Ah 0 1 0x5Bh 0 1 0x5Ch 0 1 0x5Dh 0 1 SMBUS 0x5Eh 0 1 0x5Fh 0 1 I/O Controller Hub 0x61h 0 1 Super I/O 0x63h 0 1 Local Console 0x70h 0 1 0x71h 0 1 0x72h 0 1 0x73h 0 1 Remote Console 0x78h 0 1 0x79h 0 1 0x7Ah 0 1 0x7Bh 0 1 Keyboard (only USB) 0x90h 1 0 0x91h 1 0 0x92h 1 0 0x93h 1 0 0x94h 1 0 0x96h 1 0 Mouse (only USB) 0x98h 1 0 0x99h 1 0 0x9Ah 1 0 0x9Bh 1 0 0x9Ch 1 0 Serial Port 0xA8h 1 0 0xA9h 1 0 0xAAh 1 0 1 0 0xA
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Appendix A: POST Code LED Decoder Fixed Media 0xB0h 1 0xB1h 1 Intel® Server Board S5500WB TPS 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 0 1 0 0xBCh 1 0 1 1 1 1 0xBDh 1 0 1 1 1 1 Boot Device Selection (BDS) 0xD0 1 1 0 1 0 0 0xD1 1 1 0 1 0 0 0xD2 1 1 0 1 0 0 0xD3 1 1 0 1 0 0 0xD4 1 1 0 1 0 1 0xD5 1 1 0 1 0 1 0xD6 1 1 0 1 0 1 0xDF 1 1 0 1 1 1 Pre-EFI Initialization (PEI) Core 0xE0h 1 1 1 0 0 0 0xE1h 1 1 1 0 0
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Intel® Server Board S5500WB TPS Appendix A: POST Code LED Decoder Pre-EFI Initialization Module (PEIM) / Recovery 0x30h 0 0 1 1 0 0 0 0x31h 0 0 1 1 0 0 0 0x34h 0 0 1 1 0 1 0 0x35h 0 0 1 1 0 1 0 0x36h 0 0 1 1 0 1 1 0x3Eh 0 0 1 1 1 1 1 0x3Fh 0 0 1 1 1 1 1 0 1 0 1 0 0 1 Crisis recovery initiated because of a user request Crisis recovery initiated by software (corrupt flash) Loading crisis recovery capsule Handing off control to the crisis recovery capsule Begin crisis recovery No crisis recovery capsule de
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Appendix B: Video POST Code Errors Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Error Code 8160 Error Message Processor 01 unable to apply microcode update Major 8161 Processor 02 unable to apply microcode update Major 8180 Processor 0x microcode update not found. Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure.
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Appendix B: Video POST Code Errors Intel® Server Board S5500WB TPS Error Code 8568 Error Message DIMM_E1 Component encountered a Serial Presence Detection (SPD) fail error. Major 8569 DIMM_E2 Component encountered a Serial Presence Detection (SPD) fail error. Major 856A DIMM_F1 Component encountered a Serial Presence Detection (SPD) fail error. Major 856B DIMM_F2 Component encountered a Serial Presence Detection (SPD) fail error. Major 85A0 DIMM_A1 Uncorrectable ECC error encountered.
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Intel® Server Board S5500WB TPS Appendix B: Video POST Code Errors Error Code 96E7 Error Message SMM driver component encountered a illegal software state error. Fatal 0xA000 TPM device not detected. Minor 0xA001 TPM device missing or not responding. Minor 0xA002 TPM device failure. Minor 0xA003 TPM device failed self test. Minor 0xA022 Processor component encountered a mismatch error. Major 0xA027 Processor component encountered a low voltage error.
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Glossary Intel® Server Board S5500WB TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, ―82460GX‖) with alpha entries following (for example, ―AGP 4x‖). Acronyms are then entered in their respective place, with non-acronyms following.
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Intel® Server Board S5500WB TPS Glossary Term HPA Host Physical Address Definition Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared I
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Glossary Intel® Server Board S5500WB TPS Term Definition QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) RMM3 Remote Management Module 3 SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read-Only Memory SEL Sy
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Intel® Server Board S5500WB TPS Reference Documents Reference Documents  ACPI 3.0: http://www.acpi.info/spec.htm  IPMI 2.0  Data Center Management Interface Specification v1.0, May 1, 2008: www.intel.com/go/dcmi  PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/  PCI Express* Base Specification Rev 2.0 Dec06: http://www.pcisig.com/  PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/  PMBus*: http://pmbus.org  SATA 2.