Datasheet

Revision History Intel® Server Boards S5520HC and S5500HCV TPS
Revision 1.2
Intel order number E39529-009
ii
Revision History
Date Revision
Number
Modifications
February 2008 0.1 Preliminary Draft
March 2008 0.3 Content Update
March 2008 0.5 Updated sections 2.1 and 3.2.
April 2008 0.55 Updated product code and processor support related information.
August 2008 0.6 Updated product code and memory support related information; S5500HCV
DIMM slot population change; and Chassis Intrusion header location change.
September 2008 0.65 Jumper block location change.
February 2009 1.0 Updated Block Diagram; Updated Functional Architecture Section; added BIOS
Setup Utility Section; and updated Appendix.
March 2009 1.1 – Updated Section 3.3.4.1 Memory Reservation for Memory-mapped Functions
– Updated Section 3.4.1.2 onboard SATA Storage Mode Matrix table
– Added Fan Domain Table in Section 4.3.2.2.1
– Updated Section 9.2 MTBF
– Added Appendix G Installation Guidelines
– Added Processor Stepping Mismatching on Table 2
– Updated Boot Option BIOS Setup Menu (Table 34 and Figure 36)
– Updated Table 4 Memory Running Frequency
– Updated Table 12 Intel® SAS Entry RAID Module AXX4SASMOD Storage
Mode
– Updated Table 47 and Table 48, CPU 1 and CPU2 power connectors pin-out
– Updated Table 84 POST Codes and Messages
– Updated Table 87 BMC Beep Codes
– Updated Figure 21 SMBUS Block Diagram, revised components code name
– Updated Figure 53 Power Distribution Block Diagram, revised components
code name
July 2009 1.2 – Updated Section 2.1, the feature set table
– Updated Section 3.3.2 supported memory
– Updated Section 3.3.3
– Added Section 3.15
– Updated Appendix A: adding PCI device SEL event decoding tips
– Updated Appendix G
– Updated Section 4.2.2 Keyboard, Video, and Mouse (KVM) Redirection
– Updated Table 2, Table 8, Table 9, and Table 25
– Updated Figure 13, 14