Product Service Guide

52 Intel
®
Server Board S5500BC User’s Guide
• Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are
concatenated as ACh.
Table 7. POST Progress Code LED Example
LEDs
Upper Nibble LEDs Lower Nibble LEDs
MSB LSB
LED
#7
LED
#6
LED
#5
LED
#4
LED
#3
LED
#2
LED
#1
LED
#0
8h 4h 2h 1h 8h 4h 2h 1h
Status ON OFF ON OFF ON ON OFF OFF
Results 1 0101 1 0 0
Ah Ch
Table 8. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
Checkpoint O = On, X = Off Description
Upper Nibble Lower Nibble
MSB LSB
8h 4h 2h 1h 8h 4h 2h 1h
LED #7 #6#5 #4 #3#2#1#0
Multi-use code—This POST Code is used in different contexts.
O O O O X X O X Seen at the start of
Memory Reference Code
(MRC)
Start of the very early
platform initialization code
Very late in POST, it is the
signal that the operating
system has switched to
virtual memory mode.
Memory Error Codes (accompanied by a beep code)
Note: These are codes used in early POST by the Memory Reference Code. Later in POST, these same
codes are used for other Progress Codes. (These progress codes are not controlled by the BIOS and are
subject to change at the discretion of the Memory Reference Code team.)