Technical Product Specification
Table Of Contents
- 1. Introduction
- 2. Product Overview
- 3. Functional Architecture
- 3.1 Processor Support
- 3.1.1 Processor Population Rules
- 3.1.2 Multiple Processor Initialization
- 3.1.3 Enhanced Intel SpeedStep® Technology
- 3.1.4 Intel® Extended Memory 64 Technology (Intel® EM64T)
- 3.1.5 Execute Disable Bit Feature
- 3.1.6 Multi-Core Processor Support
- 3.1.7 Intel® Virtualization Technology
- 3.1.8 Platform Environmental Control Interface (PECI)
- 3.1.9 Common Enabling Kit (CEK) Design Support
- 3.2 Intel® 5400 Memory Controller Hub Chipset (Intel® 5400 MCH Chipset)
- 3.2.1 Processor Front-Side Buses
- 3.2.2 Snoop Filter
- 3.2.3 System Memory Controller and Memory Subsystem
- 3.2.3.1 Supported Memory
- 3.2.3.2 DIMM Population Rules and Supported DIMM Configurations
- 3.2.3.3 Minimum Memory Configuration
- 3.2.3.4 Memory upgrades
- 3.2.3.5 ECC Code Support
- 3.2.3.6 Memory Sparing
- 3.2.3.7 FBD Memory Thermal Management
- 3.2.3.8 BIOS Support of Memory Subsystem
- 3.2.3.9 Memory Error Handing
- 3.2.3.10 Memory Error Reporting
- 3.3 Intel® 6321ESB I/O Controller Hub
- 3.4 PCI Subsystem
- 3.4.1 Intel® 6321ESB I/O Controller Hub PCI32: 32-bit, 33-MHz PCI Bus Segment
- 3.4.2 Intel® 6321ESB I/O Controller Hub Port 1: x4 PCI Express* Bus Segment
- 3.4.3 Intel® 6321ESB I/O Controller Hub Port 2: x4 PCI Express* Bus Segment
- 3.4.4 MCH to Intel® 6321ESB I/O Controller Hub Chip-to-Chip Interface: Two x4 PCI Express* Bus Segments
- 3.4.5 MCH Ports 5-8: x16 Gen 2 PCI Express* Bus Segment
- 3.4.6 Scan Order
- 3.4.7 Resource Assignment
- 3.4.8 Automatic IRQ Assignment
- 3.4.9 Legacy Option ROM Support
- 3.4.10 EFI PCI APIs
- 3.4.11 Legacy PCI APIs
- 3.5 Video Support
- 3.6 Network Interface Controller (NIC)
- 3.7 Super I/O
- 3.1 Processor Support
- 4. Server Management
- 4.1 Intel® 6321ESB I/O Controller Hub Integrated Baseboard Management Controller (Integrated BMC) Feature Set
- 4.2 Advanced Configuration and Power Interface (ACPI)
- 4.3 System Initialization
- 4.4 Integrated Front Panel User Interface
- 4.5 Platform Control
- 4.6 Standard Fan Management
- 4.7 Private Management I2C Buses
- 4.8 Integrated BMC Messaging Interfaces
- 4.9 Event Filtering and Alerting
- 4.10 Watchdog Timer
- 4.11 System Event Log (SEL)
- 4.12 Sensor Data Record (SDR) Repository
- 4.13 Field Replaceable Unit (FRU) Inventory Device
- 4.14 Non-maskable Interrupt (NMI)
- 4.15 General Sensor Behavior
- 4.16 Processor Sensors
- 4.16.1 Processor Status Sensors
- 4.16.2 Processor VRD Over-temperature Sensor
- 4.16.3 ThermalTrip Monitoring
- 4.16.4 Internal Error (IERR) Monitoring
- 4.16.5 Dynamic Processor Voltage Monitoring
- 4.16.6 Processor Temperature Monitoring
- 4.16.7 Processor Thermal Control Monitoring (ProcHot)
- 4.16.8 CPU Population Error Sensor
- 4.17 Intel® Remote Management Module 2 (Intel RMM2) Support
- 5. System BIOS
- 5.1 BIOS Identification String
- 5.2 BIOS User Interface
- 5.2.1 Logo/Diagnostic Screen
- 5.2.2 BIOS Setup Utility
- 5.2.3 Server Platform Setup Utility Screens
- 5.2.3.1 Main Screen
- 5.2.3.2 Advanced Screen
- 5.2.3.3 Security Screen
- 5.2.3.4 Server Management Screen
- 5.2.3.5 Server Management System Information Screen
- 5.2.3.6 Boot Options Screen
- 5.2.3.7 Boot Manager Screen
- 5.2.3.8 Error Manager Screen
- 5.2.3.9 Exit Screen
- 5.3 Loading BIOS Defaults
- 5.4 Rolling BIOS
- 5.5 OEM Binary
- 6. Connector/Header Locations and Pin-outs
- 7. Jumper Block Settings
- 8. Intel® Light-Guided Diagnostics
- 9. Power and Environmental Specifications
- 9.1 Intel® Server Board S5400SF Design Specifications
- 9.2 Server Board Power Requirements
- 9.2.1 Processor Power Support
- 9.2.2 Power Supply DC Output Requirements
- 9.2.3 Power-on Loading
- 9.2.4 Grounding
- 9.2.5 Standby Outputs
- 9.2.6 Remote Sense
- 9.2.7 Voltage Regulation
- 9.2.8 Dynamic Loading
- 9.2.9 Capacitive Loading
- 9.2.10 Closed-Loop Stability
- 9.2.11 Common Mode Noise
- 9.2.12 Ripple/Noise
- 9.2.13 Soft Starting
- 9.2.14 Timing Requirements
- 9.2.15 Residual Voltage Immunity in Standby Mode
- 10. Regulatory and Certification Information
- Appendix A: Integration and Usage Tips
- Appendix B: POST Code Diagnostic LED Decoder
- Appendix C: POST Error Messages and Handling
- Appendix D: EFI Shell Commands
- Appendix E: Supported Intel® Server Chassis
- Appendix F: 1U PCI Express* Gen 2 Riser Card
- Glossary
- Reference Documents
Intel
®
Server Board S5400SF TPS Functional Architecture
Revision 2.02
Intel order number: D92944-007
33
3.2.3.10.2 DIMM Fault Indicator LEDs
Intel
®
server boards have a fault-indicator LED next to each DIMM socket. The LEDs are turned
on when the FBDIMM on the adjacent DIMM socket is determined to be faulty.
The generic usage model for the DIMM Fault LEDs is as follows:
Table 11. DIMM Fault LED Behavior Summary
Error Event Mode of Operation Description
A FBDIMM fails Memory BIST during
POST.
N/A DIMM LED for the failing FBDIMM is
turned on.
Channel Intel
®
IBIST failure occurs
during POST.
N/A If there are multiple FBDIMMs on
that channel, all corresponding
failing DIMM LEDs are turned on.
Correctable error threshold reached for
a failing FBDIMM. (Ten correctable
errors occur on the same FBDIMM
within the limits of the error period.)
System is operating in the single-
channel mode.
DIMM fault LED for the failed
FBDIMM is turned on when the error
count reaches the threshold (i.e, on
the tenth error).
Correctable error threshold reached for
a failing FBDIMM. (Ten correctable
errors occur on the same FBDIMM
within the limits of the error period.)
System is operating in the dual-
channel mode.
DIMM fault LED for the failed
FBDIMM is turned on when the error
count reaches the threshold (i.e., on
the tenth error).
Uncorrectable error occurs on a
FBDIMM.
System is operating in the single-
channel mode.
DIMM fault LED for the failed
FBDIMM is turned on.
Uncorrectable error occurs on a
FBDIMM.
System is operating in the dual-
channel mode.
DIMM fault LEDs for the failed pair
of FBDIMMs are turned on.
Fatal channel link-level or FBD fatal
error occurs.
N/A DIMM fault LEDs of all FBDIMMs
present on the failing channel or
branch are turned on.
Note: As indicated in the preceding table, when two FBDIMMs are operating in lthe ock-stepped
mode and one of the FBDIMMs fails, the BIOS also lights the DIMM Fault LED of the
companion FBDIMM. This is because the BIOS cannot isolate failures at the individual FBDIMM
level in this mode.
3.3 Intel
®
6321ESB I/O Controller Hub
The Intel
®
6321ESB I/O Controller Hub is a multi-function device that provides four distinct
functions: an I/O Controller, a PCI-X Bridge, a Gigabit Ethernet Controller, and an Integrated
Baseboard Management Controller (Integrated BMC). Each function within the Intel
®
6321ESB
I/O Controller Hub has its own set of configuration registers. Once configured, each appears to
the system as a distinct hardware controller.
A primary role of the Intel
®
6321ESB I/O Controller Hub is to provide the gateway to all PC-
compatible I/O devices and features. The server board uses the following Intel
®
6321ESB I/O
Controller Hub features:
Six-channel SATA interface with SATA Busy LED Control
Dual GbE MAC
Integrated Baseboard Management Controller (Integrated BMC)
Single ATA interface, with Ultra DMA 100 capability
Universal Serial Bus (USB) 2.0 interface