Technical Product Specification

Table Of Contents

Intel

Server Board S5400SF TPS Functional Architecture

Revision 2.02

Intel order number: D92944-007

3.2.3.8.4 Memory Interleaving

In general, to optimize memory accesses, the BIOS enables Branch Interleaving, which allows

the chipset to interleave data for successive cache-lines between the autonomous branches.

Additionally, the Intel

5400 MCH Chipset also provides interleaving across logical memory

devices called ranks. A pair of single-ranked lock-stepped FBDIMMs constitutes a memory rank.

Interleaving effected between ranks allows the chipset to interleave cache-line data between

participant ranks, and the process is called Rank Interleaving. The BIOS by default enables 4:1

Rank Interleaving, in which 4 ranks participate in a single cache-line access.

3.2.3.8.5 Support for Mixed Speed Memory Modules

The BIOS supports memory modules of mixed speed by automatic selection of the highest

common frequency of all memory modules (FBDIMM).

To program a FBDIMM to function correctly for a given frequency, the BIOS queries each

FBDIMM’s Serial-presence Data (SPD) store. The SPD contains the frequency characteristics

of the FBDIMM, which are measured in terms of the following parameters:

 CAS latency (CL)

 Common clock frequency

 Additive latency (AL)

 Buffer read delay (BRD)

The CAS latency and the additive latency are configurable parameters that are detected by the

BIOS by reading the SPD data of the FBDIMMs. The BRD is the average inherent delay that is

caused by the finite time that the AMB consumes in buffering the data read from the DRAMs

before forwarding it on the Northbound (or Southbound) path.

3.2.3.9 Memory Error Handing

The BIOS classifies memory errors into the following categories:

 Correctable ECC errors: These are errors that occur between the Northbridge MCH and

the DRAM memory cells and are corrected by the chipset. This correction could be the

result of ECC correction, a successfully retried memory cycle, or both.

 Uncorrectable ECC errors: These are errors that occur in the memory cells and result in

data corruption. The chipset’s ECC engine detects these errors, but cannot correct them.

These errors create a loss of data fidelity and are severe errors.

 Unrecoverable and Fatal Errors: These are errors that are outside the scope of the

standard ECC engine. These errors are thermal errors, certain FBD channel errors and

data path errors. These errors bring about catastrophic failure of the system.

There are two specific stages in which memory errors can occur:

 Early POST during memory discovery

 Late POST or at runtime (when the operating system is running)